Advance Information Page 7 of 112 DEC 2009 REVISION 1.02 7.2.4 BUS PARKING .........." />
參數(shù)資料
型號(hào)： PI7C8154ANAE
廠商： Pericom
文件頁(yè)數(shù)： 82/114頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
標(biāo)準(zhǔn)包裝： 27
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應(yīng)商設(shè)備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類(lèi)型： 表面貼裝
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PI7C8154A
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 7 of 112
DEC 2009 REVISION 1.02
7.2.4
BUS PARKING ..............................................................................................................................67
8
GENERAL PURPOSE I/O INTERFACE ...............................................................................................67
8.1
GPIO CONTROL REGISTERS.........................................................................................................68
8.2
SECONDARY CLOCK CONTROL..................................................................................................68
8.3
LIVE INSERTION .............................................................................................................................70
9
EEPROM INTERFACE............................................................................................................................70
9.1
AUTO MODE EEPROM ACCESS ...................................................................................................70
9.2
EEPROM MODE AT RESET............................................................................................................71
9.3
EEPROM DATA STRUCTURE........................................................................................................71
9.4
EEPROM CONTENT ........................................................................................................................71
10
VITAL PRODUCT DATA (VPD) ............................................................................................................72
11
CLOCKS.....................................................................................................................................................72
11.1
PRIMARY AND SECONDARY CLOCK INPUTS..........................................................................72
11.2
SECONDARY CLOCK OUTPUTS ..................................................................................................72
12
PCI POWER MANAGEMENT................................................................................................................72
13
RESET.........................................................................................................................................................74
13.1
PRIMARY INTERFACE RESET ......................................................................................................74
13.2
SECONDARY INTERFACE RESET................................................................................................74
13.3
CHIP RESET......................................................................................................................................75
14
CONFIGURATION REGISTERS ...........................................................................................................76
14.1.1
SIGNAL TYPES.........................................................................................................................77
14.1.2
VENDOR ID REGISTER – OFFSET 00h .................................................................................77
14.1.3
DEVICE ID REGISTER – OFFSET 00h ...................................................................................77
14.1.4
COMMAND REGISTER – OFFSET 04h ..................................................................................77
14.1.5
STATUS REGISTER – OFFEST 04h.........................................................................................78
14.1.6
REVISION ID REGISTER – OFFSET 08h................................................................................79
14.1.7
CLASS CODE REGISTER – OFFSET 08h ...............................................................................79
14.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch ......................................................................79
14.1.9
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.......................................................79
14.1.10
HEADER TYPE REGISTER – OFFSET 0Ch............................................................................80
14.1.11
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ............................................................80
14.1.12
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ......................................................80
14.1.13
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ..................................................80
14.1.14
SECONDARY LATENCY TIMER – OFFSET 18h ....................................................................80
14.1.15
I/O BASE REGISTER – OFFSET 1Ch ......................................................................................80
14.1.16
I/O LIMIT REGISTER – OFFSET 1Ch .....................................................................................81
14.1.17
SECONDARY STATUS REGISTER – OFFSET 1Ch ................................................................81
14.1.18
MEMORY BASE REGISTER – OFFSET 20h ...........................................................................82
14.1.19
MEMORY LIMIT REGISTER – OFFSET 20h ..........................................................................82
14.1.20
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ...........................82
14.1.21
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..........................83
14.1.22
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h83
14.1.23
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch
83
14.1.24
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .........................................83
14.1.25
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................83
14.1.26
CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................84
14.1.27
INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................84
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8154ANAE-33 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154B 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE
PI7C8154BNA 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C8154BNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154BNAE-80 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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