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參數(shù)資料
| 型號： | PI74ALVCH16260 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs |
| 中文描述： | 12位到24位復(fù)用D類鎖存器與三態(tài)輸出 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 280K |
| 代理商： | PI74ALVCH16260 |
1
PS8089C 04/17/01
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with 3-State Outputs
Logic Block Diagram
G1
OE2B
C1
1D
1B1
TO 11 OTHER CHANNELS
OE1B
OEA
A1
LE1B
LE2B
LEA1B
LEA2B
SEL
1
1
C1
1D
C1
1D
C1
1D
2B1
23
6
28
8
1
29
56
55
30
27
2
Product Features
PI74ALVCH16260 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at 40°C to +85°C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 2.3V to 3.6 V
CC
operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing
address and data information in microprocessor or bus-interface
and in memory-interleaving.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
for address and/or data transfer. The output-enable (OE1B, OE2B,
and OEA) inputs control bus transceiver functions. The OE1B and
OE2B control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
To ensure high-impedance state during power up or power down,
OE should be tied to V
CC
through a pullup resistor whose minimum
value is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI74ALVCH162601 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic | 18-Bit Universal Bus Transceiver w/Resistor |
| PI74ALVCH162601A | 功能描述:IC UNIV BUS TXRX 18BIT 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCH 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| PI74ALVCH162601V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| PI74ALVCH16260A | 功能描述:IC 12/14-BIT MUX/LATCH 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 鎖銷 系列:74ALVCH 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標準包裝:1,500 系列:74VCX 邏輯類型:D 型透明鎖存器 電路:8:8 輸出類型:三態(tài) 電源電壓:1.8 V ~ 3.6 V 獨立電路:2 延遲時間 - 傳輸:1.5ns 輸出電流高，低:6mA，6mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| PI74ALVCH16260A56 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Bus Exchanger |
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