參數(shù)資料
型號(hào): PI6LC4831AZBIEX
廠(chǎng)商: PERICOM SEMICONDUCTOR CORP
元件分類(lèi): PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, QCC56
封裝: 8 X 8 MM, GREEN, MO-137AE, TQFN-56
文件頁(yè)數(shù): 2/14頁(yè)
文件大?。?/td> 891K
代理商: PI6LC4831AZBIEX
10
www.pericom.com
P-0.1
03/28/11
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PI6LC4831A
Crystal to Differential HCSL/LVCMOS Frequency Synthesizer
AC Characteristics (table notes continued from previous page)
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Only valid within the VCO operating range.
NOTE 3: Spread Spectrum clocking enabled.
NOTE 4: Measurement taken from differential waveform.
NOTE 5: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to
droop back into the VRB ±100mV differential range.
NOTE 6: Measurement taken from single-ended waveform.
NOTE 7: Defined as the maximum instantaneous voltage including overshoot.
NOTE 8: Defined as the minimum instantaneous voltage including undershoot.
NOTE 9: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx+ equals the falling edge of Qx–.
NOTE 10: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Refers to all crossing points for this measurement.
NOTE 11: Defined as the total variation of all crossing voltage of Rising Qx+ and Falling Qx–. This is the maximum allowed variance in the VCROSS for
any particular system.
NOTE 12: Measured from -150mV to +150mV on the differential waveform (derived from Qx+ minus Qx–). The signal must be monotonic through the
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
Configuration
Rs
33
5%
Rs
33
5%
Rp
49.9
1%
475
1%
Rp
49.9
1%
2pF
5%
2pF
5%
Clock#
Clock
TLA
TLB
PI6LC4831A
Configuration test load board termination for HCSL Outputs
11-0032
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