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參數(shù)資料
| 型號： | PI6CU877 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | PLL Clock Driver for 1.8V DDR2 Memory |
| 中文描述： | PLL時鐘驅(qū)動器1.8V的DDR2內(nèi)存 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PI6CU877 |
6
PS8689B 08/05/04
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
(15)
Parameter
Description
Diagram
AV
DD
, V
DDQ
= 1.8V ±0.1V
Min.
Nom.
Units
Max.
8
8
40
-40
50
50
40
40
75
4
ten
tdis
OE to and Y/Y
OE to and Y/Y
see Fig 11
see Fig 11
ns
tjit(cc+)
tjit(cc-)
t()
t()dyn
tsk(o)
tjit(per)
tjit(hper)
Cycle-to-cycle jitter
see Fig 4
0
0
ps
Static phase offset
(11)
Dynamic phase offset
Output clock skew
Period jitter
(12)
Halk period jitter
(12)
Input clock slew rate
Output enable (OE)
Output clock slew rate
(14, 16)
see Fig 5
see Fig 10
see Fig 6
see Fig 7
see Fig 8
see Fig 9
see Fig 9
see Fig 1, 9
-50
-50
-40
-75
1
0.5
1.5
slr(i)
2.5
V/ns
slr(o)
2.5
3
V
OX
Outpu differenital-pair cross voltage
(13)
see Fig 2
(V
DDQ
/2)
-0.1
(V
DDQ
/2)
+0.1
V
The PLL on the PI6CU877 is capable of meeting all the above test parameters while supporting SSC synthesirers
with the following parameters:
SSC modulation frequency
SSC clock input frequency deviation
PI6CU877 PLL design should target the values below to minimize the SCC induced skew:
PLL Loop Bandwidth
30.00
0.00
33
kHz
%
-0.50
2.0
MHz
Notes:
11. Static Phase Offset does not include Jitter
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
13. VOX specified at the DRAM clock input or the test load.
14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used.
16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6CU877NF | PLL Clock Driver for 1.8V DDR2 Memory |
| PI6CU877NFE | PLL Clock Driver for 1.8V DDR2 Memory |
| PI6CVF857ZDE | 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CVF857NF | 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CVF857 | 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CU877NF | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 125MHz to 300MHz 52-Pin VFBGA |
| PI6CU877NFE | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CU877NFEX | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CU877NFX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 125MHz to 300MHz 52-Pin VFBGA T/R |
| PI6CUA877NFE | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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