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參數(shù)資料
| 型號： | PI6C2952FBE |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Low Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 80K |
| 代理商： | PI6C2952FBE |
1
PS8542A 01/30-06
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PI6C2952
Description
The PI6C2952 is a 3.3V compatible, PLL-based clock driver device
targeted for high-performance clock applications. The device fea-
tures a fully integrated PLL with no external components
required. With output frequencies up to 180MHz and eleven low-
skew outputs, the PI6C2952 is well suited for high-performance
designs. The device employs a fully differential PLL design to
optimize jitter and noise rejection performance.
The PI6C2952 features three banks of individually configurable
outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The
internal divide circuitry allows for output frequency ratios of 1:1, 2:1,
3:1, and 3:2:1. The output frequency relationship is controlled by the
fsel frequency control pins. The fsel pins and other inputs are
LVCMOS/LVTTL compatible inputs.
The PI6C2952 uses external feedback to the PLL. This features
allows the device to be used as a “zero delay” buffer. Any of the
eleven outputs can be used as feedback to the PLL. To optimize PLL
stability and jitter performance,the VCO_Sel pin allows for the
choice of two VCO ranges. For board level test, the MR/OE pin
allows a user to force the outputs into high impedance. For system
debug, the PI6C2952’s PLL can be bypassed. When forced to a logic
HIGH, the PL_LEN input routes the signal on the RefClk input
around the PLL directly to the internal dividers. Because the signal
is routed through the dividers, it may take several transitions of the
RefClk to affect a transition on the outputs. This features allows a
designer to single step the design for debug purposes.
The PI6C2952’s outputs are LVCMOS which are optimally designed
to drive terminated transmission lines. For applications using series-
terminated transmission lines, each PI6C2952 output can drive two
lines. This capability provides an effective fanout of 22, more than
enough clocks for most clock tree designs.
Features
±100ps Cycle-to-Cycle Jitter
Fully Integrated PLL
Output Frequency up to 180MHz
High-Impedance Disabled Outputs
Compatible with PowerPC, Intel, and High-Performance
RISC Microprocessors
Configurable Output Frequency
32-Pin LQFP Package (FB)
Pin Configuration
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
VCCO
Qb2
Qb3
GNDO
GNDO
Qc0
Qc1
VCCO
G
Q
Q
V
V
Q
Q
G
V
f
f
f
M
R
G
F
VCCO
Qa2
Qa1
GNDO
Qa0
VCCI
VCCA
PLL_En
32-Pin
FB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C3991-IJ | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991-5IJ | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991-5J | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991 | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991J | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2952FBEX | 功能描述:鎖相環(huán) - PLL 180MHZ 3Bank 11Output ZDB RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2952FBX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 32-Pin LQFP T/R |
| PI6C2972 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Low Voltage PLL Clock Driver |
| PI6C2972FC | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI6C2972FCE | 功能描述:鎖相環(huán) - PLL Zero Delay Buffer with Divider RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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