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參數(shù)資料
| 型號(hào)： | PI6C3991-5J |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| 中文描述： | 3.3V的高速，低電壓偏差可編程時(shí)鐘緩沖器SuperClock |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 500K |
| 代理商： | PI6C3991-5J |
1
PS8450B 04/09/01
Features
All output pair skew <100ps typical (250 Max.)
3.75 MHz to 80 MHz output operation
User-selectable output functions
Selectable skew to 18ns
Inverted and Non-Inverted
Operation at and input frequency
Operation at 2X and 4X input frequency
(input as low as 3.75 MHz, x4 operation)
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50-ohm terminated lines
Operates from a single 3.3V supply
Low operating current
Available in 32-pin PLCC (J) package
Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-perfor-
mance computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated trans-
mission lines with impedances as low as 50 ohms while delivering
minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal zero skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow
distribution of a low-frequency clock that can be multiplied by
two or four at the clock destination. This feature allows flexibility
and simplifies system timing distribution design for complex
high-speed systems.
Logic Block Diagram
Pin Configuration
1Q0
1Q1
1F0
1F1
2Q0
2Q1
2F0
2F1
3Q0
3Q1
3F0
3F1
4Q0
4Q1
4F0
4F1
Select Inputs
(three level)
Matrix
Select
Skew
Test
Filter
Phase
Freq.
DET
FB
REF
VCO and
Time Unit
Generator
FS
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PI6C3991
3.3V High-Speed, Low-Voltage
Programmable Skew Clock Buffer
SuperClock
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3
3
V
C
F
V
C
2
2
3
F
V
C
R
G
T
2
4
3
2
1
32 31
30
14 15 16 17 18 19
20
32-Pin
J
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C3991 | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3991J | 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock |
| PI6C3Q991-2J | 3.3V Programmable Skew PLL Clock Driver |
| PI6C39911A | No RSENSE Current Mode Synchronous Step-Down Switching Regulator; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PI6C39911A-2 | Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C3991-5JE | 功能描述:鎖相環(huán) - PLL Programmable Skew Zero Delay RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C3991-5JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| PI6C3991A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 750ps Accuracy. 3.3V. LVTTL. 3.75 to 80 MHz |
| PI6C3991A-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 80 MHz |
| PI6C3991A-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 500ps Accuracy. 3.3V. LVTTL. 3.75 to 80 MHz |
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