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參數(shù)資料
| 型號(hào)： | PI6C2510ALE |
| 廠(chǎng)商： | Pericom |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DVR 10OUT 24-TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 類(lèi)型： | PLL 時(shí)鐘驅(qū)動(dòng)器 |
| PLL： | 帶旁路 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
1
PS8306C
11/13/08
Product Pin Configuration
Functional Table
Logic Block Diagram
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PI6C2510A
Phase-Lock Loop Clock Driver
with 10-Clock Outputs
Description
The PI6C2510A family is a low-skew, low-jitter, phase-lock loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing one clock input to one bank of ten outputs,
with an output enable.
The PI6C2510A is designed to meet PC100 SDRAM Registered
DIMM Specification, for heavy load applications. For test pur-
poses, the PLL can be bypassed by strapping AVCC to ground.
The PI6C2510A family has the same pinouts as TI’s CDC2510A/
2510B, with enhanced rise/fall times, and allowing a Spread Spec-
trum clock input.
Features
High-Performance Phase-Lock Loop Clock Distribution that
meets 100/134 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
Allows Clock Input to have Spread Spectrum modulation for
EMI reduction
Zero Input-to-Output delay: Distribute One Clock Input
to one bank of ten outputs, with an output enable.
Same pinout as TI CDC2510/2510A
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V VCC
Wide Clock Frequency Range:
Packaging
-24-pin TSSOP (L)
s
t
u
p
n
Is
t
u
p
t
u
O
GN
I
_
K
L
C]
9
:
0
[
Y
1T
U
O
_
B
F
XL
L
LH
L
H
HH
H
G
10
CLK_IN
FB_IN
PLL
AVCC
FB_OUT
1Y[0:9]
CLK_IN
AVCC
VCC
1Y9
1Y8
GND
1Y7
1Y6
1Y5
VCC
FB_IN
AGND
VCC
1Y0
1Y1
1Y2
GND
1Y3
1Y4
VCC
G
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24-Pin
L
08-0298
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2510ALEX | 功能描述:鎖相環(huán) - PLL 3.3v PLL Clock Drivr RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2510ALX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 25MHz to 125MHz 24-Pin TSSOP T/R |
| PI6C2516 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 16 Clock Outputs |
| PI6C2516A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 16 Clock Outputs |
| PI6C2520 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Clock IC | 135 MHz. 20 Output Zero-Delay Clock Driver |
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