參數(shù)資料
型號: PI6C39911JE
廠商: Pericom
文件頁數(shù): 1/11頁
文件大?。?/td> 0K
描述: IC PROG SKEW CLOCK DRIVER 32PLCC
產(chǎn)品變化通告: Product Discontinuation 03/Oct/2011
標(biāo)準(zhǔn)包裝: 32
系列: SuperClock®
類型: 時鐘緩沖器
PLL:
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/無
頻率 - 最大: 133MHz
除法器/乘法器: 是/是
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 32-PLCC(11.43x13.97)
包裝: 管件
1
PS8497I
11/06/08
Features
All output pair skew <100ps typical (250 Max.)
12.5 MHz to 133 MHz output operation
3.125 MHz to 133 MHz input operation (input as low as 3.125
MHz for 4x operation, or 6.25 MHz for 2x operation)
User-selectable output functions
— Selectable skew to 18ns
— Inverted and non-inverted
— Operation at and input frequency
— Operation at 2X and 4X input frequency
Zero input-to-output delay
50% duty-cycle outputs
Inputs are 5V Tolerant
LVTTL outputs drive 50-Ohm terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package (available in pb-free and green)
Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C39911 offers selectable control over system clock func-
tions. These multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50-Ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Logic Block Diagram
PinConfiguration
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3Q1
3Q0
V
CCN
FB
V
CCN
2Q1
2Q0
3F0
FS
V
CCQ
REF
GND
TEST
2F1
4321 32 31 30
14 15 16 17 18 19 20
PI6C39911
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer - SuperClock
32 Pin
J
1Q0
1Q1
1F0
1F1
2Q0
2Q1
2F0
2F1
3Q0
3Q1
3F0
3F1
4Q0
4Q1
4F0
4F1
Select Inputs
(three level)
Matrix
Select
Skew
Test
Filter
Phase
Freq.
DET
FB
REF
FS
VCO and
Time Unit
Generator
08-0298
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