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參數(shù)資料
| 型號(hào)： | PI6C2401WE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 97 |
| 類(lèi)型： | PLL 時(shí)鐘驅(qū)動(dòng)器 |
| PLL： | 帶旁路 |
| 輸入： | TTL |
| 輸出： | TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 134MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
1
PS8419D
11/13/08
1
2
3
AVCC
4
CLK_OUT
CLK_IN
GND
FB_IN
8
7
6
5
AGND
VCC
S
Product Pin Configuration
Logic Block Diagram
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PI6C2401
Product Features
High-Performance Phase-Locked-Loop Clock Distribution for
Networking, ATM, 100/134 MHz Registered DIMM Synchro-
nous DRAM modules for server/workstation/PC applications
Zero Input-to-Output delay
Lowjitter:Cycle-to-Cyclejitter ±100psmax.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V VCC
Packaged in Plastic 8-pin SOIC Package (W)
Pb-free and Green Available
Wide range of Clock Frequencies
Phase-Locked Loop Clock Driver
Product Description
The PI6C2401 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Application
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-
to-device skew introduced can significantly reduce
the performance. Pericom recommends the use of a zero-delay
buffer and an eighteen output non-zero-delay buffer . As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clocks Signal and 17 Outputs
17
Zero Delay
Buffer
PI6C2401
Reference
Clock
Signal
CLK_OUT
Feedback
18 Output
Non-Zero
Delay
Buffer
V
Se
c
r
u
o
S
t
u
p
t
u
On
w
o
d
t
u
h
S
L
P
1L
L
PN
0N
I
_
K
L
CY
Control Input
CLK_IN
FB_IN
S
PLL
CLK_OUT
8-Pin
W
08-0298
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C2402WE | IC PLL CLOCK DRIVER 8-SOIC |
| PI6C2405A-1WIE | IC 1:5 0-DELAY CLOCK BUFF 8-SOIC |
| PI6C2408-4WIE | IC 4+4 0-DELAY CLK BUFF 16-SOIC |
| PI6C2409-1WE | IC 4+4+1 0-DELAY CLK BUFF 16SOIC |
| PI6C2501AWE | IC PLL CLOCK DRIVER 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2401WEX | 功能描述:鎖相環(huán) - PLL 3.3v Zero Delay Driver RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2402 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Clock IC | 1 Output Zero-Delay Clock Driver w/ Ext. Loopback. 2X Multiplier |
| PI6C2402WE | 功能描述:鎖相環(huán) - PLL 3.3v Zero Delay Clock RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2402WEX | 功能描述:鎖相環(huán) - PLL 3.3v Zero Delay Driver RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2404A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:Zero-Delay Clock Buffer |
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