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參數(shù)資料
| 型號： | PI0256HSN |
| 英文描述： | 25-レm-Pitch Wide Aperture Spectroscopic Photodiode Arrays |
| 中文描述： | 25 -レ米間距寬孔徑光譜光電二極管陣列 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 555K |
| 代理商： | PI0256HSN |
PI0256HSN, PI0512HSN, PI1024HSN
Engineering Data Sheet
Page 4 of 8
March 13, 2002
I/O Pins
Besides the VSS and VDD supply pins, there are 9
functionally active I/O pins. Only two clocks, CLK and
START, are required for controlling the timing of the
sensor's video readout. One additional digital input,
ADDCAP controls the bank of capacitors as described
in the Selectable Charge Capacity section above. The
digital output, EOS, marks the end of the line-scan.
The charge output pin, QOUT, is typically connected to
a charge-integrating amplifier that is biased to Vbias
(see Recommended Operating Conditions section
below). For normal anti-blooming operation, the ABG
requires a 0.1-μF capacitor connected to VSS and the
ABD is also biased to Vbias. Each temperature diode
is operated with a small constant current that forward-
biases its PN junction. By measuring the forward-bias
voltage, one can track the silicon die temperature. The
temperature diodes may be disabled by connecting
their anodes to VSS. These I/Os are listed with their
acronym designators and functional descriptions in the
following Table 1.
Table 1. Symbols and functions and I/O pins.
Symbol
VSS
VDD
START
CLK
ADDCAP
EOS
QOUT
ABG
Function and Description
Ground.
+5.0 Volts.
Start Pulse: Input to start the line scan.
Clock Pulse: Input to clock the shift register.
Add Capacitors: Input that selects the bank of capacitors to increase charge capacity.
End Of Scan: Output from the shift register to indicate the completion of one line scan.
Video Charge Output: Output from the photodiodes pixels.
Anti-Blooming Gate: Self-biased gate for setting anti-blooming level. Requires 0.1-μF
connected to VSS.
Anti-Blooming Drain: Bias for anti-blooming drain. Set to Vbias.
Temperature Diode 1: Anode of temperature diode 1.
Temperature Diode 2: Anode of temperature diode 2.
No Connection
ABD
TD1
TD2
NC
Figure 5. Simplified circuit diagram of a HSN photodiode array. The diagram does not include the capacitor bank
and the anti-blooming circuitry.
CLK
ART
TD1
SHIFT REGISTER
EOS
QOUT
TD2
VSS
D
D
D
D
P
P
P
P
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