參數(shù)資料
型號： PHD11N03LT
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管)
中文描述： 10.3 A, 30 V, 0.15 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝： PLASTIC, DPAK-3
文件頁數(shù)： 1/11頁
文件大?。?/td> 105K
代理商： PHD11N03LT
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHB11N03LT, PHD11N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 30 V
’Trench’
technology
Low on-state resistance
Fast switching
Logic level compatible
I
D
= 10.5 A
R
DS(ON)
≤
150 m
(V
GS
= 5 V)
R
DS(ON)
≤
130 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channelenhancement mode,logic level, field-effectpower transistor in aplastic envelopeusing ’
trench
’technology.
Applications:-
d.c. to d.c. converters
switched mode power supplies
The PHB11N03LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD11N03LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
SOT428 (DPAK)
SOT404 (D
2
PAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
V
GSM
Pulsed gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
15
±
20
10.3
7.3
41
33
175
UNIT
V
V
V
V
A
A
A
W
C
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
I
DM
P
D
T
j
, T
stg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
d
g
s
1
3
tab
2
1
2
3
tab
1
It is not possible to make contact to pin 2 of the SOT404 or SOT428 package
September 1999
1
Rev 1.000
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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