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| 型號： | PHASE |
| 英文描述： | Phase Lock Loop Configurations (1757k) |
| 中文描述： | 鎖相環(huán)配置（1757k） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE |
Revision 1.01/April 2002 Semtech Corp.
Page 3
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
1
Introduction
This Application Note describes some examples of the ways in which the ACS8530 Phase Lock Loops
(PLL) can be configured for different frequency and output jitter options. The ACS8530 has two
independent PLL "paths" on the same chip, one denoted the T0 path and the other the T4 path. The T0
path is a combination of a Digital PLL (DPLL) and an Analog PLL (APLL). The T4 path is also a combination
of a DPLL and an APLL, but the DPLL can be configured to function independently from the APLL. The T0
path is a high quality, highly configurable path designed to provide features necessary for node timing
synchronization within a SONET/SDH network. The T4 path is a simpler and less configurable path
designed to give a totally independent path for internal equipment synchronization. The device supports
use of either or both paths, either locked together or independent. The basic PLL architecture of the
ACS8530 is shown in Figure 1.
2
General
A DPLL gives a stable and consistent level of performance that can be easily programmed for different
dynamic behaviour or operating range. Digital synthesis is used to generate all required SONET/SDH
output frequencies. The digital logic operates at 204.8 MHz that is multiplied up from the external 12.8
MHz oscillator module. Hence the best resolution of the output signals from the DPLL is one 204.8 MHz
cycle or 4.9 ns. Additional resolution and lower final output jitter is provided by a de-jittering APLL that
reduces the 4.9 ns pk-pk jitter from the digital down to 350 ps pk-pk and 50-60 ps RMS as typical final
outputs measured broadband (from 10 Hz to 1 GHz). This arrangement combines the advantages of the
flexibility and repeatability of a DPLL with the low jitter of an APLL.
Figure 1
ACS8530 PLL Architecture
PFD and
Loop Filter
Forward
DFS
Feedback
DFS
F8530D_017BLOCKDIA_04
TO8 /TO9
TO1 to TO7
PFD and
Loop Filter
Feedback
DFS
77M
Forward
DFS
77M
Output
DFS
LF
Output
DFS
T4
Output
APLL
T4
Output
Dividers
T0
Output
APLL
T0
Feedback
APLL
T0
Output
Dividers
1
0
0
1
0
1
0
1
1
1
0
0
T4 DPLL
T0 DPLL
Analog
Reference
Input
Reference
Input
T4_Dig_Feedback
T0_DPLL_Freq
T4_APLL_for_T0
Lock_T4_to_T0
Control
T4_DPLL_Frequency
Sts_Current_Phase
Sts_Current_Phase
T4_Op_From_TO
8 kHz
T0_DPLL_Frequency
Control
T0_DPLL_Frequency
Control
PBO
Phase
Offset
Locking
Frequency
TO1 to TO7
TO1 to TO7
TO10/TO11
Locking
Frequency
T4
T0
0
1
0
1
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