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參數(shù)資料
| 型號： | PGA309AIPWT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | GREEN, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 661K |
| 代理商： | PGA309AIPWT |
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
EXC
GND
A
V
SA
V
IN1
V
IN2
V
FB
V
OUT
V
SJ
TEST
V
SD
GND
D
PRG
SCL
SDA
TEMP
IN
REF /REF
IN
OUT
SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011
www.ti.com
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(TOP VIEW)
PIN DESCRIPTIONS
PIN NO.
NAME
DESCRIPTION
Bridge sensor excitation. Connect to bridge if linearization and/or internal reference for bridge excitation
1
VEXC
is to be used.
2
GNDA
Analog ground. Connect to analog ground return path for VSA. Should be same as GNDD.
3
VSA
Analog voltage supply. Connect to analog voltage supply. To be within 200mV of VSD.
Signal input voltage 1. Connect to + or – output of sensor bridge. Internal multiplexer can change
4
VIN1
connection internally to Front-End PGA.
Signal input voltage 2. Connect to + or – output of sensor bridge. Internal multiplexer can change
5
VIN2
connection internally to Front-End PGA.
VOUT feedback pin. Voltage feedback sense point for over/under-scale limit circuitry. When internal gain
set resistors for the output amplifier are used, this is also the voltage feedback sense point for the
6
VFB
output amplifier. VFB in combination with VSJ allows for ease of external filter and protection circuits
without degrading the PGA309 VOUT accuracy. VFB must always be connected to either VOUT or the
point of feedback for VOUT, if external protection is used.
7
VOUT
Analog output voltage of conditioned sensor.
Output amplifier summing junction. Use for output amplifier compensation when driving large capacitive
8
VSJ
loads (> 100pF) and/or for using external gain setting resistors for the output amplifier.
9
TEST
Test/External controller mode pin. Pull to GNDD in normal mode.
10
VSD
Digital voltage supply. Connect to digital voltage supply. To be within 200mV of VSA.
11
GNDD
Digital ground. Connect to digital ground return path for VSD. Should be same as GNDA.
Single-wire interface program pin. UART-type interface for digital calibration of the PGA309 over a
12
PRG
single wire. Can be connected to VOUT for a three-lead (VS, GND, VOUT) digitally-programmable sensor
assembly.
Clock input/output for Two-Wire, industry-standard compatible interface for reading and writing digital
13
SCL
calibration and configuration from external EEPROM. Can also communicate directly to the registers in
the PGA309 through the Two-Wire, industry-standard compatible interface.
Data input/output for Two-Wire, industry-standard compatible interface for reading and writing digital
14
SDA
calibration and configuration from external EEPROM. Can also communicate directly to the registers in
the PGA309 through the Two-Wire, industry-standard compatible interface.
External temperature signal input. PGA309 can be configured to read a bridge current sense resistor
as an indicator of bridge temperature, or an external temperature sensing device such as diode
junction, RTD, or thermistor. This input can be internally gained by 1, 2, 4, or 8. In addition, this input
15
TEMPIN
can be read differentially with respect to VGNDA, VEXC, or the internal/external VREF. There is also an
internal, register-selectable, 7mA current source (ITEMP) that can be connected to TEMPIN as an RTD,
thermistor, or diode excitation source.
Reference input/output pin. As an output, the internal reference (selectable as 2.5V or 4.096V) is
16
REFIN/REFOUT
available for system use on this pin. As an input, the internal reference may be disabled and an
external reference can then be applied as the reference for the PGA309.
8
Copyright 2003–2011, Texas Instruments Incorporated
Product Folder Link(s): PGA309
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