參數(shù)資料
型號： PGA309AIPWT
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO16
封裝： GREEN, PLASTIC, TSSOP-16
文件頁數(shù)： 18/24頁
文件大?。?/td> 661K
代理商： PGA309AIPWT
www.ti.com
SBOS292C – DECEMBER 2003 – REVISED JANUARY 2011
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.
At TA = +25°C, VSA= VSD = +5V (VSA = VSUPPLY ANALOG, VSD = VSUPPLY DIGITAL; VSA must equal VSD), GNDD = GNDA = 0, and VREF
= REFIN/REFOUT = +5V, unless otherwise noted.
PGA309
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Front-End PGA + Output Amplifier
VOUT/VIN Differential Signal Gain Range
(1)
Fine gain adjust = 1
8 to 1152
V/V
Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128
Output Amplifier gains: 2, 2.4, 3, 3.6, 4.5, 6, 9
Input Voltage Noise Density
f = 1kHz
210
nV/
√Hz
VOUT Slew Rate
0.5
V/ms
VOUT Settling Time (0.01%)
VOUT/VIN Differential gain = 8, RL = 5kΩ || 200pF
6
ms
VOUT Settling Time (0.01%)
VOUT/VIN Differential gain = 191, RL = 5kΩ || 200pF
4.1
ms
VOUT Nonlinearity
0.002
%FSR
External Sensor Output Sensitivity
VSA = VSD = VEXC = +5V
1 to 245
mV/V
Front-End PGA
Auto-Zero Internal Frequency
7
kHz
Offset Voltage (RTI)
(2)
Coarse offset adjust disabled
±3
±50
mV
vs Temperature
±0.2
mV/°C
vs Supply Voltage, VSA
±2
mV/V
vs Common-Mode Voltage
GF = Front-End PGA gain
1500/GF
6000/GF
mV/V
Linear Input Voltage Range
(3)
0.2
VSA 1.5
V
Input Bias Current
0.1
1.5
nA
Input Impedance: Differential
30 || 6
G
Ω || pF
Input Impedance: Common-Mode
50 || 20
G
Ω || pF
Input Voltage Noise
0.1Hz to 10Hz, GF = 128
4
mVPP
PGA Gain
Gain Range Steps
4, 8, 16, 23.27, 32, 42.67, 64, 128
4 to 128
V/V
Initial Gain Error
GF = 4 to 42
0.2
±1
%
GF = 64
0.25
±1.2
%
GF = 128
0.3
±1.6
%
vs Temperature
10
ppm/°C
Output Voltage Range
0.05 to VSA 0.1
V
Bandwidth
Gain = 4
400
kHz
Gain = 128
60
kHz
Coarse Offset Adjust
(RTI of Front-End PGA)
Range
±(14)(VREF)(0.00085)
±56
±59.5
±64
mV
vs Temperature
0.004
%/°C
Drift
±14 steps, 4-bit + sign
4
mV
Fine Offset Adjust (Zero DAC)
(RTO of the Front-End PGA)
(2)
Programming Range
0
VREF
V
Output Voltage Range
0.1
VSA – 0.1
V
Resolution
65,536 steps, 16-bit DAC
73
mV
Integral Nonlinearity
20
LSB
Differential Nonlinearity
0.5
LSB
Gain Error
0.1
%
Gain Error Drift
10
ppm/°C
Offset
5
mV
Offset Drift
10
mV/°C
(1)
PGA309 total differential gain from input (VIN1 – VIN2) to output (VOUT). VOUT / (VIN1 – VIN2) = (Front-end PGA gain) × (Output Amplifier
gain) × (Gain DAC).
(2)
RTI = Referred-to-input. RTO = referred to output.
(3)
Linear input range is the allowed min/max voltage on the VIN1 and VIN2 pins for the input PGA to continue to operate in a linear region.
The allowed common-mode and differential voltage depends on gain and offset settings. Refer to the Gain Scaling section for more
information.
Copyright 2003–2011, Texas Instruments Incorporated
3
Product Folder Link(s): PGA309
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