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參數(shù)資料
| 型號： | PF48F4444PPVBQ0 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 64M X 16 FLASH 1.8V PROM, 88 ns, PBGA80 |
| 封裝： | 11 X 11 MM, 1.40 MM HEIGHT, LEAD FREE, SCSP-88/80 |
| 文件頁數(shù)： | 46/102頁 |
| 文件大小： | 1609K |
| 代理商： | PF48F4444PPVBQ0 |
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1-Gbit P30 Family
April 2005
46
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
8.0
Power and Reset Specifications
8.1
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If
VCCQ and/or VPP are not connected to the VCC supply, then V
CC
should attain V
CCMIN
before
applying V
CCQ
and V
PP
. Device inputs should not be driven before supply voltage equals V
CCMIN
.
Power supply transitions should only occur when RST# is low. This protects the device from
accidental programming or erasure during power transitions.
8.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase devices because
systems typically expect to read from flash memory when coming out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU initialization may not occur. This is because the
flash memory may be providing status information, instead of array data as expected. Connect
RST# to the same active low reset signal used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs during
power-up/down. Invalid bus conditions are masked, providing a level of memory protection.
Num Symbol
P1
t
PLPH
Parameter
Min
100
-
-
60
Max
-
25
25
-
Unit
ns
Notes
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
V
CC
Power valid to RST# de-assertion (high)
P2
t
PLRH
μs
P3
t
VCCPH
Notes:
1.
2.
3.
4.
5.
6.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
is < t
PLPH
MIN, but this is not guaranteed.
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
If RST# is tied to the V
supply, device will not be ready until t
after V
≥
V
.
If RST# is tied to any supply/signal with V
CCQ
voltage levels, the RST# input voltage must not exceed
V
until V
≥
V
.
Reset completes within t
PLPH
if RST# is asserted while no erase or program operation is executing.
7.
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| PF48F2P0VBQ0 | Intel StrataFlash Embedded Memory |
| PF48F3P0VBQ0 | Intel StrataFlash Embedded Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PF48F4444PPVTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F4P0VB00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F4P0VBQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F4P0VT00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F4P0VTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
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