<big id="hhdan"><dfn id="hhdan"></dfn></big>
<ins id="hhdan"></ins>
<tfoot id="hhdan"></tfoot>
<nobr id="hhdan"><menu id="hhdan"></menu></nobr>
  • <ins id="hhdan"><small id="hhdan"><label id="hhdan"></label></small></ins>
    <ins id="hhdan"><menu id="hhdan"></menu></ins>
    參數(shù)資料
    型號(hào): PF48F4000P0ZTQ0
    廠商: INTEL CORP
    元件分類: PROM
    英文描述: Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; Number of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle
    中文描述: 16M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
    封裝: 8 X 11 MM, 1 MM HEIGHT, LEAD FREE, SCSP-88
    文件頁數(shù): 52/102頁
    文件大小: 1609K
    代理商: PF48F4000P0ZTQ0
    1-Gbit P30 Family
    April 2005
    52
    Intel StrataFlash
    Embedded Memory (P30)
    Order Number: 306666, Revision: 001
    Datasheet
    Write
    0x10
    Alternate Word
    Program Setup
    Equivalent to the Word Program Setup command, 0x40.
    0xE8
    Buffered Program
    This command loads a variable number of words up to the buffer size of 32
    words onto the program buffer.
    The confirm command is Issued after the data streaming for writing into the
    buffer is done. This instructs the WSM to perform the Buffered Program
    algorithm, writing the data from the buffer to the flash memory array.
    First cycle of a 2-cycle command; initiates Buffered Enhanced Factory
    Program mode (BEFP). The CUI then waits for the BEFP Confirm command,
    0xD0, that initiates the BEFP algorithm. All other commands are ignored when
    BEFP mode begins.
    If the previous command was BEFP Setup (0x80), the CUI latches the address
    and data, and prepares the device for BEFP mode.
    First cycle of a 2-cycle command; prepares the CUI for a block-erase
    operation. The WSM performs the erase algorithm on the block addressed by
    the Erase Confirm command. If the next command
    is not
    the Erase Confirm
    (0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and
    places the device in read status register mode.
    If the first command was Block Erase Setup (0x20), the CUI latches the
    address and data, and the WSM erases the addressed block. During block-
    erase operations, the device responds only to Read Status Register and Erase
    Suspend commands. CE# or OE# must be toggled to update the Status
    Register in asynchronous read. CE# or ADV# must be toggled to update the
    Status Register Data for synchronous Non-array reads
    This command issued to any device address initiates a suspend of the
    currently-executing program or block erase operation. The Status Register
    indicates successful suspend operation by setting either SR[2] (program
    suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write
    State Machine remains in the suspend mode regardless of control signal states
    (except for RST# asserted).
    This command issued to any device address resumes the suspended program
    or block-erase operation.
    First cycle of a 2-cycle command; prepares the CUI for block lock configuration
    changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0),
    or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5],
    indicating a command sequence error.
    If the previous command was Block Lock Setup (0x60), the addressed block is
    locked.
    If the previous command was Block Lock Setup (0x60), the addressed block is
    unlocked. If the addressed block is in a lock-down state, the operation has no
    effect.
    If the previous command was Block Lock Setup (0x60), the addressed block is
    locked down.
    First cycle of a 2-cycle command; prepares the device for a Protection Register
    or Lock Register program operation. The second cycle latches the register
    address and data, and starts the programming algorithm
    First cycle of a 2-cycle command; prepares the CUI for device read
    configuration. If the Set Read Configuration Register command (0x03) is not
    the next command, the CUI sets Status Register bits SR[4] and SR[5],
    indicating a command sequence error.
    If the previous command was Read Configuration Register Setup (0x60), the
    CUI latches the address and writes A[15:0] to the Read Configuration Register.
    Following a Configure Read Configuration Register command, subsequent
    read operations access array data.
    0xD0
    Buffered Program
    Confirm
    0x80
    BEFP Setup
    0xD0
    BEFP Confirm
    Erase
    0x20
    Block Erase Setup
    0xD0
    Block Erase Confirm
    Suspend
    0xB0
    Program or Erase
    Suspend
    0xD0
    Suspend Resume
    Block Locking/
    Unlocking
    0x60
    Lock Block Setup
    0x01
    Lock Block
    0xD0
    Unlock Block
    0x2F
    Lock-Down Block
    Protection
    0xC0
    Program Protection
    Register Setup
    Configuration
    0x60
    Read Configuration
    Register Setup
    0x03
    Read Configuration
    Register
    Table 21.
    Command Codes and Definitions (Sheet 2 of 2)
    Mode
    Code
    Device Mode
    Description
    相關(guān)PDF資料
    PDF描述
    PF48F0P0ZTQ0 Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket; Insert Arrangement:10-98
    PF48F2P0ZTQ0 Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle
    PF48F3P0ZTQ0 Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Pin; Insert Arrangement:12-10
    PF48F4P0ZTQ0 Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle
    PF48F0P0ZT00 Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:41; Connector Shell Size:20; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket; Insert Arrangement:20-41
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PF48F4000P0ZTQ0A 功能描述:IC FLASH 256MBIT 100NS 88-SCSP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步,DDR II 存儲(chǔ)容量:18M(1M x 18) 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA(13x15) 包裝:托盤 其它名稱:71P71804S200BQ
    PF48F4000P0ZTQE3 功能描述:IC FLASH 256MBIT 100NS 88SCSP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:512M(64M x 8) 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP(0.724",18.40mm 寬) 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
    PF48F4000P0ZTQED 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 256Mbit 16M x 16bit 110ns 64-Pin EZBGA Tray
    PF48F4000P0ZTQEJ 功能描述:IC FLASH 256MBIT SCSP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M(2M x 8,1M x 16) 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA(6x8) 包裝:帶卷 (TR)
    PF48F4400M0Y0B0 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx Wireless Flash Memory (W18) with AD Multiplexed IO