- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369995 > PF48F4000P0ZBQ0 (INTEL CORP) Intel StrataFlash Embedded Memory PDF資料下載
參數(shù)資料
| 型號： | PF48F4000P0ZBQ0 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 88 ns, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, LEAD FREE, SCSP-88 |
| 文件頁數(shù)： | 61/102頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | PF48F4000P0ZBQ0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
61
11.0
Programming Operations
The device supports three programming methods: Word Programming (40h/10h), Buffered
Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h). See
Section
9.0, “Device Operations” on page 48
for details on the various programming commands issued to
the device. The following sections describe device programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is locked down,
WP# must be deasserted and the block must be unlocked before attempting to program the block.
Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and
termination of the operation. See
Section 13.0, “Security Modes” on page 69
for details on locking
and unlocking blocks.
The Intel StrataFlash Embedded Memory (P30) is segmented into multiple Programming
Regions. Programming Regions are made up of 8 or 16 blocks depending on the density. The 64-
and 128-Mbit devices have 8 blocks per Programming Region, while the 256-Mbit has 16 blocks in
each Programming Region (see
Table 26
). See
Section 4.4, “Memory Maps” on page 24
for
address ranges of each Programming Region per density.
Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory.
XIP applications must partition the memory such that code and data are in separate programming
regions (see
Table 26, “Programming Regions per Device” on page 61
). Each Programming
Region should contain only code or data, and not both. The following terms define the difference
between code and data. System designs must use these definitions when partitioning their code and
data for the P30 device.
11.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup command to the
device (see
Section 9.0, “Device Operations” on page 48
). This is followed by a second write to the
device with the address and data to be programmed. The device outputs Status Register data when
read. See
Figure 40, “Word Program Flowchart” on page 85
. V
PP
must be above V
PPLK
, and within
the specified V
PPL
min/max values (nominally 1.8 V).
Table 26.
Programming Regions per Device
Device Density
Number of blocks per
Programming Region
Number of Programming
Regions per Device
64-Mbit
8 blocks
8
128-Mbit
8 blocks
16
256-Mbit
16 blocks
16
512-Mbit
16 blocks
32
1-Gbit
16 blocks
64
Code :
Execution code ran out of the flash device on a continuous basis in the system.
Data :
Information periodically programmed into the flash device and read back (e.g.
execution code shadowed and executed in RAM, pictures, log files, etc.).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PF48F0P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F2P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F3P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F4P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F4P0VB00 | Photoelectric Sensor; Sensor Input Type:Optical; Sensing Range Max:43mm; Sensor Output Type:Relay; Leaded Process Compatible:No; Output Type:Relay; Peak Reflow Compatible (260 C):No; Contact Current Max:3A; Contact Rating:3A |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PF48F4000P0ZBQ0A | 功能描述:IC FLASH 256MBIT 100NS 88-SCSP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| PF48F4000P0ZBQE3 | 功能描述:IC FLASH 256MBIT 100NS 88SCSP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| PF48F4000P0ZBQEA | 功能描述:256MB P30-HV 65NM QUAD+ LF BB RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| PF48F4000P0ZBQEF | 功能描述:IC FLASH 256MBIT SCSP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| PF48F4000P0ZBQEG | 制造商:Micron Technology Inc 功能描述:16MX16 NOR FLASH PLASTIC PBF V 制造商:Micron Technology Inc 功能描述:PF48F4000P0ZBQEG - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。