- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367901 > PEF2445N ?Multipoint Switching and Conferencing Unit - Attenuation? PDF資料下載
參數(shù)資料
| 型號(hào)： | PEF2445N |
| 英文描述： | ?Multipoint Switching and Conferencing Unit - Attenuation? |
| 中文描述： | ？多點(diǎn)交換和會(huì)議股-衰減？ |
| 文件頁(yè)數(shù)： | 16/73頁(yè) |
| 文件大?。?/td> | 1618K |
| 代理商： | PEF2445N |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)
PEB 2466
PEF 2466
Pin Descriptions
Hardware Reference Manual
7
2001-02-20
21
GNDD
I
Digital Ground
Ground reference for all digital signals.
Internally isolated from GNDA1,2,3,4.
Master Clock Input
1536, 2048, 4096 or 8192 kHz must be applied for any
operation (selected in Register XR5).
MCLK, PCLK, FSC must be synchronous.
Reset Input
Forces the device to default setting mode; active low.
Digital Supply Voltage
+5 V supply for digital circuits (use 100 nF blocking cap.).
Transmit Control Output A
PCM Interface: active if data is transmitted via DXA;
active low, open drain.
Data Transmit to PCM-Highway A
PCM Interface: PCM data for each channel is transmitted
in 8-bit bursts every 125 μs.
Data Receive from PCM-Highway A
PCM Interface: PCM data for each channel is received in
8-bit bursts every 125 μs.
Transmit Control Output B
PCM Interface: active if data is transmitted via DXB;
active low, open drain.
Data Transmit to PCM-highway B
PCM Interface: data for each channel is transmitted in
8-bit bursts every 125 μs.
Data Receive from PCM-highway B
PCM Interface: data for each channel is received in 8-bit
bursts every 125 μs.
Frame Synchronization Clock
8 kHz; reference for individual time slots, indicates start of
PCM frame; MCLK, PCLK, FSC must be synchronous.
PCM Data Clock
128 to 8192 kHz; determines the rate at which PCM data
is shifted into or out of the PCM-ports.
MCLK, PCLK, FSC must be synchronous.
all
22
MCLK
I
all
23
RESET#
I
all
24
V
DDD
I
all
25
TCA#
O
all
26
DXA
O
all
27
DRA
I
all
28
TCB#
O
all
29
DXB
O
all
30
DRB
I
all
31
FSC
I
all
32
PCLK
I
all
Pin
Symbol
Type Function
Ch.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PEF24622 | ?SOCRATES-4? |
| PEF2466-H | A-Law/u-Law CODEC |
| PEF24901 | ISDN LINE INTERFACE|BASIC|CMOS|QFP|64PIN|PLASTIC |
| PEF24901H | ?Quad ISDN Echocancellation Circuit Digital Front-End for 4B3T Line Code? |
| PEF24902 | ISDN Line Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEF24470HV1.3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PEF24471EV1.3 | 制造商:Lantiq 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Infineon Technologies AG 功能描述: |
| PEF24471EV1.3-G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T/E RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| PEF24471E-V12 | 制造商:Infineon Technologies AG 功能描述: |
| PEF24622 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?SOCRATES-4? |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。