參數(shù)資料
型號: PEB24902
廠商: SIEMENS A G
元件分類: 數(shù)字傳輸電路
英文描述: Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP64
文件頁數(shù): 44/50頁
文件大小: 502K
代理商: PEB24902
PEB 24902
PEF 24902
Digital Interface
Semiconductor Group
44
05.96
4.3
Boundary Scan Timing
Figure 21
Boundary Scan Timing
1)
This specification is only applicable in case of the usage of the internal PLL/oscillator or if a sinusoidal
clock is provided at XIN. It is valid 1ms after power on (free running mode).
Table 18
Dynamic Output Characteristics
Parameter
Signal
Symbol
Limit Values
min.
typ.
Unit
max.
10
Clock rise / fall time CL15
Clock period
1)
Pulse width
1)
high / low
Data delay
t
r
, t
f
t
cw
t
h
t
l
t
D
ns
ns
ns
ns
ns
CL15
CL15
65
20
20
PDM,
SDR
20
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