參數(shù)資料
型號: PEB24902
廠商: SIEMENS A G
元件分類: 數(shù)字傳輸電路
英文描述: Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP64
文件頁數(shù): 29/50頁
文件大小: 502K
代理商: PEB24902
PEB 24902
PEF 24902
Technical Description
Semiconductor Group
29
05.96
The signal to noise plus distortion ratio is measured using an evenly distributed but
otherwise random sequence of +3, +1, -1, -3 (2B1Q code) or +1, 0, -1 (4B3T code)
driving 98
in series with a DC voltage. The output signal at AOUT and BOUT has to be
weighted with a low pass filter from 0 to 80 kHz (2B1Q code) or 120 kHz (4B3T code),
respectively, to get the specified sum of noise and total harmonic distortion as given in
table 6
. Any linear mismatch between 3 and 1 symbols is cancelled for the S/N
measurements.
3.2.4
For the 2B1Q-code and the 4B3T-code different external hybrids are suggested in
figures 13
and
14
. These hybrids will work correctly with an according transformer as
described in
table 7
. Please note that table 7 gives typical transformer parameters and
is not intended to be a complete transformer description. Transformer linearity must be
such that no significant destortion is added to the signal passing the echo path from
AOUT/BOUT to AIN/BIN.
External Hybrid and Transformer Parameters
Peak-to-peak output jitter
measured with a high-pass filter
of 30 Hz cut-off frequency
Peak-to-peak output jitter
measured without the high-pass
filter
Signal / (Noise + Distortion)
driving 98
in series with 6.8
V DC
Signal / (Noise + Distortion)
driving 98
in series with 3.2
V DC
Signal / (Noise + Distortion)
driving 98
in series with 0.5
V DC
Corner frequency of the DAC RC
low pass filter
Output Impedance AOUTx/
BOUTx
1.3
nsec jitter free 15.36
MHz clock
6.5
nsec
26
dB
53
dB
63
68
dB
420
620
900
kHz
1
2
6
4
12
Power-Up
Power-Down
Table 6
Specified Data of the Digital-to-Analogue-Converter
(cont’d)
Parameter
Limit Values
typ.
Unit Test Condition
min.
max.
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