參數資料
型號： PEB2466-H
英文描述： LTC3409 Evaluation Kit
中文描述： A-Law/u-Law編解碼器
文件頁數： 17/73頁
文件大?。?/td> 1618K
代理商： PEB2466-H
PEB 2466
PEF 2466
Pin Descriptions
Hardware Reference Manual
8
2001-02-20
33
CHCLK1
O
Chopper Clock Output 1
Provides programmable (2
…
28 ms) output signal
(synchronous to MCLK).
Interrupt Output, Channels 1 and 2
Active high.
Signaling Input Channel 1, Pin 1
Signaling Input Channel 1, Pin 0
Bi-directional Signaling, Channel 1 Pin 2
Bi-directional Signaling, Channel 1 Pin 1
Bi-directional Signaling, Channel 1 Pin 0
Signaling Output, Channel 1, Pin 1
Signaling Output, Channel 1, Pin 0
Signaling Output, Channel 2, Pin 0
Signaling Output, Channel 2, Pin 1
Bi-directional Signaling, Channel 2 Pin 0
Bi-directional Signaling, Channel 2 Pin 1
Bi-directional Signaling, Channel 2 Pin 2
Signaling Input, Channel 2, Pin 0
Signaling Input, Channel 2, Pin 1
Analog Voice (Voltage) Input, Channel 1
Requires a coupling capacitor >39 nF to the SLIC.
Analog Ground, Channel 1
Not internally connected to GNDD or GNDA2,3,4.
Analog Voice (Voltage) Output, Channel 1
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC
’
s input impedance.
(See Chapter
5.1 Analog Interface
)
Analog Supply Voltage
,
Channels 1 and 2
+5 V (100 nF blocking capacitor required).
Analog Voice (Voltage) Output, Channel 2
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC
’
s input impedance.
(See Chapter
5.1 Analog Interface
)
all
34
INT12
O
1, 2
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SI1_1
SI1_0
SB1_2
SB1_1
SB1_0
SO1_1
SO1_0
SO2_0
SO2_1
SB2_0
SB2_1
SB2_2
SI2_0
SI2_1
I
I
1
1
1
1
1
1
1
2
2
2
2
2
2
2
I/O
I/O
I/O
O
O
O
O
I/O
I/O
I/O
I
I
49
V
IN1
I
1
50
GNDA1
I
1
51
V
OUT1
O
1
52
V
DDA12
I
1, 2
53
V
OUT2
O
2
Pin
Symbol
Type Function
Ch.
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相關代理商/技術參數
參數描述
PEB2466-HV1.2 制造商:Siemens 功能描述:A/MU-LAW, PCM CODEC, PQFP64
PEB2466HV1.3 制造商:Rochester Electronics LLC 功能描述:- Bulk
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