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參數(shù)資料
| 型號： | PE97632 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | 3.2 GHz的Δ-Σ調(diào)制的低相位噪聲應用分數(shù)N頻率合成器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 373K |
| 代理商： | PE97632 |
Advance Information
PE97632
Page 7 of 16
Document No. 70-0205-02
│
www.psemi.com
2006 Peregrine Semiconductor Corp. All rights reserved.
Table 6. AC Characteristics
V
DD
= 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Control Interface and Latches (see Figures 3, 4)
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Main Divider (Including Prescaler) (Note 4)
Operating frequency
Input level range
Main Divider (Prescaler Bypassed) (Note 4)
Operating frequency
Input level range
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
(Note 1)
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
10
10
30
30
30
30
30
F
in
P
Fin
275
-5
3200
5
MHz
dBm
External AC coupling
F
in
P
Fin
50
-5
300
5
MHz
dBm
External AC coupling
Reference Divider
(Note 3)
Single ended input
Phase Detector
(Note 3)
f
r
P
fr
Operating frequency
Reference input power (Note 2)
100
MHz
dBm
-2
f
c
Comparison frequency
50
MHz
SSB Phase Noise (F
in
= 1.9 GHz, f
r
= 20 MHz, f
c
= 20 MHz, LBW = 50 kHz, V
DD
= 3.3 V, Temp = 25° C
)
(Note 4)
Phase Noise
Phase Noise
Φ
N
Φ
N
1 kHz Offset
10 kHz Offset
-97
-102
dBc/Hz
dBc/Hz
Note 1:
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3:
Parameter is guaranteed through characterization only and is not tested.
f
clk
is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify f
clk
specification.
Note 4:
Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow.
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| PE97632ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
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| PE9763ES | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
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