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參數(shù)資料
| 型號(hào)： | PE43503MLI-Z |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 983K |
| 描述： | IC RF DSA 5BIT 50 OHM 24QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | UltraCMOS™, HaRP™ |
| 衰減值： | 0dB ~ 31dB |
| 容差： | ±0.3dB |
| 頻率范圍： | 9kHz ~ 6GHz |
| 阻抗： | 50 歐姆 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 其它名稱： | PE43503 |
Product Specification
PE43503
Page 2 of 11
?008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0252-05 UltraCMOS" RFIC Solutions
-1
0
1
2
0
4
8
12
16
20
24
28
32
200MHz
900MHz
1800MHz
2200MHz
3000MHz
4000MHz
5000MHz
6000MHz
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
4
8
12
16
20
24
28
32
Attenuation Setting (dB)
200MHz
900MHz
1800MHz
2200MHz
3000MHz
4000MHz
5000MHz
6000MHz
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
1000
2000
3000
4000
5000
6000
Frequency (GHz)
1dB State
2dB State
4dB State
8dB State
16dB State
31dB State
900 MHz
2200 MHz
3800 MHz
5800 MHz
5
10
15
20
25
30
0
35
5
10
15
20
25
30
0
35
Attenuation State
ttenuation
Table 1. Electrical Specifications @ +25癈, V
DD
= 3.3 V or 5.0 V
Performance Plots
Parameter
Test Conditions
Frequency
Min.
Typical
Max.
Units
Frequency Range
9 kHz
6 GHz
Attenuation Range
1 dB Step
0 31
dB
Insertion Loss
9 kHz d 6 GHz
2.4
2.9
dB
Attenuation Error
0dB - 31dB Attenuation settings
0dB - 21dB Attenuation settings
22dB - 31dB Attenuation settings
0dB - 31dB Attenuation settings
9 kHz d 4 GHz
4 GHz d 6 GHz
4 GHz d 6 GHz
4 GHz d 6 GHz
?0.3+3%)
+0.4+9%
+2.4+0%
-0.2-3%
dB
dB
dB
dB
Relative Phase
All States
9 kHz d 6 GHz
72
?
P1dB
(note 1)
Input
20 MHz - 6 GHz
30
32
dBm
Input IP3
Two tones at +18 dBm, 20 MHz spacing
20 MHz 6 GHz
+58
dBm
Return Loss
DC d 6 GHz
17
dB
Switching Speed
50% DC CTRL to 10% / 90% RF
650
ns
Typical Spurious Value
1 MHz
-115
dBm
Video Feed Through
10
mVpp
Settling Time
RF settled to within 0.05 dB of final value
RBW = 5 MHz, Averaging ON.
4
祍
RF Trise/Tfall
10% / 90% RF
400
ns
*Monotonicity is held so long as Step-Error does not cross below -1
Figure 3. 1dB Step Error vs. Frequency *
Figure 4. 1dB Attenuation vs. Attenuation State
Figure 5. 1dB Major State Bit Error
Figure 6. 1dB Attenuation Error vs. Frequency
Note 1. Please note Maximum Operating Pin (50&) of +23dBm as shown in Table 3.
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