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參數(shù)資料
| 型號(hào)： | PE43503MLI-Z |
| 廠商： | Peregrine Semiconductor |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 983K |
| 描述： | IC RF DSA 5BIT 50 OHM 24QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | UltraCMOS™, HaRP™ |
| 衰減值： | 0dB ~ 31dB |
| 容差： | ±0.3dB |
| 頻率范圍： | 9kHz ~ 6GHz |
| 阻抗： | 50 歐姆 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 其它名稱： | PE43503 |
Page 1 of 11
Document No. 70-0252-05 www.psemi.com
?008-2009 Peregrine Semiconductor Corp. All rights reserved.
The PE43503 is a HaRP"-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA) covering a 31 dB attenuation
range in 1 dB steps. The Peregrine 50& RF DSA provides a
serial CMOS control interface. It maintains high attenuation
accuracy over frequency and temperature and exhibits very low
insertion loss and low power consumption. Performance does
not change with Vdd due to on-board regulator. This next
generation Peregrine DSA is available in a 4x4 mm 24-lead
QFN footprint.
The PE43503 is manufactured on Peregrines UltraCMOS"
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Product Specification
50 & RF Digital Attenuator
5-bit, 31 dB, 9 kHz - 6.0 GHz
Product Description
Figure 2. Functional Schematic Diagram
PE43503
Features
" HaRP"-enhanced UltraCMOS" device
" Attenuation: 1 dB steps to 31 dB
" High Linearity: Typical +58 dBm IP3
" Excellent low-frequency performance
" 3.3 V or 5.0 V Power Supply Voltage
" Fast switch settling time
" Programming Modes:
" Direct Parallel
" Latched Parallel
" Serial
" High-attenuation state @ power-up (PUP)
" CMOS Compatible
" No DC blocking capacitors required
" Packaged in a 24-lead 4x4x0.85 mm QFN
Figure 1. Package Type
Control Logic Interface
RF Input
RF Output
Switched Attenuator Array
Serial In
LE
CLK
A0
A1
A2
Parallel Control
5
P/S
24-lead 4x4x0.85 mm QFN Package
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