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參數(shù)資料
| 型號： | PE4302-51 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 50 OHM RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| 中文描述： | 50歐姆射頻數(shù)字衰減器6位，31.5分貝，直流4.0千兆赫 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 456K |
| 代理商： | PE4302-51 |
Product Specification
PE4302
Page 7 of 11
Document No. 70/0056~02D
│
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4302 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of
the internal negative voltage generator is desired,
then connect –VDD (Black banana plug) to
ground. If an external –VDD is desired, then apply
-3V.
J1 should be connected to the parallel port of a
PC with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the Power Up options, first disconnect
the parallel ribbon cable from the evaluation
board. The parallel cable must be removed to
prevent the PC parallel port from biasing the
control pins.
During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
attenuation is set to the value present on the six
control bits on the six parallel data inputs (C0.5 to
C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (Figure
16) will eliminate package resonance between the
RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Figure 15. Evaluation Board Layout
Figure 16. Evaluation Board Schematic
Z=50 Ohm
PUP2
J5
SMA
1
C2
C16
CLK
100 pF
DATA
C4
C0.5
10k
10k
C8
Z=50 Ohm
PUP1
PS
C1
VDD
U1
MLPQ4X4
1
2
3
4
5
6
7
8
9
1
11
12
13
14
15
1
1
1
1
2
C16
RFin
DATA
CLK
LE
V
P
P
V
G
GND
Vss/GND
PS
RFout
C8
C
C
G
C
C
LE
J4
SMA
1
Note: Resistors on pins 1 and 3 are required to avoid package
resonance and meet error specifications over frequency.
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PE4302-51SA | 制造商:Peregrine Semiconductor 功能描述:ATTENUATOR - DIGITALLY CONTROLLED |
| PE4302-52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:50 OHM RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| PE4302DS | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| PE4302-EK | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| PE4304 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:75 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC - 2.0 GHz |
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