參數(shù)資料
型號(hào): PE4302-51
廠商: Electronic Theatre Controls, Inc.
英文描述: 50 OHM RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ
中文描述: 50歐姆射頻數(shù)字衰減器6位,31.5分貝,直流4.0千兆赫
文件頁(yè)數(shù): 5/11頁(yè)
文件大小: 456K
代理商: PE4302-51
Product Specification
PE4302
Page 5 of 11
Document No. 70/0056~02D
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Table 4. DC Electrical Specifications
Note 1:
Both RF ports must be held at 0 V
DC
or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k
resistor to V
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 k
resistor in series, as close to pin as possible
to avoid frequency resonance.
Figure 14. Pin Configuration (Top View)
V
D
P
P
V
D
G
1
2
1
1
1
1
15
14
13
12
11
6
7
8
9
1
2
3
4
5
C16
RF1
Data
Clock
LE
GND
Vss/GND
P/S
RF2
C8
C
C
G
C
C
20-lead QFN
4x4mm
Exposed Solder Pad
Pin
No.
1
Pin
Name
C16
Description
Attenuation control bit, 16dB (Note 4).
2
RF1
RF port (Note 1).
3
Data
Serial interface data input (Note 4).
4
Clock
Serial interface clock input.
5
LE
Latch Enable input (Note 2).
6
V
DD
Power supply pin.
7
PUP1
Power-up selection bit, MSB.
8
PUP2
Power-up selection bit, LSB.
9
V
DD
Power supply pin.
10
GND
Ground connection.
11
GND
Ground connection.
12
V
ss
/GND
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
13
P/S
14
RF2
RF port (Note 1).
15
C8
Attenuation control bit, 8 dB.
16
C4
Attenuation control bit, 4 dB.
17
C2
Attenuation control bit, 2 dB.
18
GND
Ground connection.
19
C1
Attenuation control bit, 1 dB.
20
C0.5
Attenuation control bit, 0.5 dB.
Paddle
GND
Ground for proper operation
Symbol
Parameter/Conditions
Min
Max
Units
V
DD
Power supply voltage
-0.3
4.0
V
+
0.3
150
V
V
I
Voltage on any input
-0.3
V
T
ST
Storage temperature range
Operating temperature
range
Input power (50
)
ESD voltage (Human Body
Model)
-65
°C
T
OP
-40
85
°C
P
IN
24
dBm
V
ESD
500
V
Parameter
Min
Typ
Max
Units
V
Power Supply
Voltage
I
Power Supply
Current
Digital Input High
2.7
3.0
3.3
V
100
μ
A
0.7xV
DD
V
Digital Input Low
0.3xV
DD
1
V
Digital Input Leakage
μ
A
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Switching Frequency
The PE4302 has a maximum 25kHz switching
rate.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (see
Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
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