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參數(shù)資料
| 型號(hào)： | PE33361MLIAA-Z |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, QFN-48 |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 344K |
| 代理商： | PE33361MLIAA-Z |
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Advance Information
PE33361
Page 2 of 15
2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0287-01
│ UltraCMOS RFIC Solutions
Table 1. Pin Descriptions
Figure 2. Pin Configurations (Top View)
Figure 3. Package Type
Pin No.
Pin Name
Interface Mode
Type
Description
1
D0
Parallel
Input
Parallel data bus bit0 (LSB).
M0
Direct
Input
M Counter bit0 (LSB).
2
D1
Parallel
Input
Parallel data bus bit1.
M1
Direct
Input
M Counter bit1.
3
D2
Parallel
Input
Parallel data bus bit2.
M2
Direct
Input
M Counter bit2.
4
D3
Parallel
Input
Parallel data bus bit3.
M3
Direct
Input
M Counter bit3.
5
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
6
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
7
S_WR
Serial
Input
Serial load enable input. While S_WR is “l(fā)ow”, Sdata can be serially clocked.
Primary register data is transferred to the secondary register on S_WR or Hop_WR
rising edge.
D4
Parallel
Input
Parallel data bus bit4
M4
Direct
Input
M Counter bit4
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Input
Parallel data bus bit5.
M5
Direct
Input
M Counter bit5.
8
48-lead QFN (RoHS-Compliant)
D
0, M0
D
1, M1
D
2, M2
D
3, M3
V
DD
V
DD
S_WR, D
4, M4
Sdata, D
5, M5
Sclk, D
6, M6
FSELS, D
7, Pre_enB
GND
f
p
V
DD_fp
D
out
V
DD
C
ext
V
DD
PD_DB
PD_UB
V
DD_fc
f
c
F
in
B
F
in
H
op_
W
R
A_
W
R
M1
_W
R
V
DD
B
m
od
eB
S
m
od
e,
A
3
M
2_W
R
,A
2
E_
W
R
,A
1
FSELP, A
0
GN
D
R
3
R
2
R
1
R
0
V
DD
E
nhB
LD
fr
GN
D
GN
D
V
DD
GN
D
N/C
GN
D
41
42
43
44
45
46
47
40 39 38 37
48
20
19
18
17
16
15
14
21 22 23 24
13
5
6
7
8
9
10
11
4
3
2
1
12
32
31
30
29
28
27
26
33
34
35
36
25
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