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參數(shù)資料
| 型號(hào)： | PDU138-5 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138) |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大小： | 59K |
| 代理商： | PDU138-5 |
PDU138
Doc #02004
5/6/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
1.5V (Rising & Falling)
5.0V
±
0.1V
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PW
IN
= 1.5 x Total Delay
PER
IN
= 4.5 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
Timing Diagram For Testing
TD
AR
TD
AF
PER
IN
PW
IN
T
RISE
T
FALL
0.6V
0.6V
2.4V
1.5V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDU138-50 | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138) |
| PDU13F-.5 | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
| PDU13F-.5A2 | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
| PDU13F-.5B2 | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
| PDU13F-.5M | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU-138-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU138-50 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138) |
| PDU-138-50M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU-138-5M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| PDU13F | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
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