- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄369989 > PDU13F-.5M (DATA DELAY DEVICES INC) 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) PDF資料下載
參數(shù)資料
| 型號(hào)： | PDU13F-.5M |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
| 中文描述： | PASSIVE DELAY LINE, COMPLEMENTARY OUTPUT, DIP14 |
| 封裝： | DIP-14 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 163K |
| 代理商： | PDU13F-.5M |
PDU13F
3-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU13F)
data
delay
devices,
inc.
3
FEATURES
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Two separate outputs: inverting & non-inverting
Precise and stable delays
Input & outputs fully TTL interfaced & buffered
10 T
2
L fan-out capability
Fits standard 14-pin DIP socket
Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU13F-series device is a 3-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A2-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (EN/) is held LOW during
normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH
states, respectively. The address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance:
5% or 1ns,
whichever is greater
Inherent delay (TD
0
):
6ns typical (OUT)
5.5ns typical (OUT/)
Setup time and propagation delay:
Address to input setup (T
AIS
):
6ns
Disable to output delay (T
DISO
):
6ns typ. (OUT)
Operating temperature:
0
°
to 70
°
C
Temperature coefficient:
100PPM/
°
C (excludes TD
0
)
Supply voltage V
CC
:
5VDC
±
5%
Supply current:
I
CCH
= 45ma
I
CCL
= 20ma
Minimum pulse width:
20% of total delay
PACKAGES
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
N/C
N/C
OUT
OUT/
EN/
GND
VCC
N/C
N/C
N/C
A0
A1
A2
PDU13F-xx
PDU13F-xxA2 Gull-Wing
PDU13F-xxB2 J-Lead
PDU13F-xxM
DIP
Military DIP
PDU13F-xxMC3
Military Gull-Wing
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN
N/C
N/C
N/C
OUT
OUT/
EN/
GND
VCC
N/C
N/C
N/C
A0
A1
A2
N/C
PIN DESCRIPTIONS
IN
Delay Line Input
OUT Non-inverted Output
OUT/ Inverted Output
A2
Address Bit 2
A1
Address Bit 1
A0
Address Bit 0
EN/
Output Enable
VCC +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Per Step (ns)
PDU13F-.5
.5
±
.3
PDU13F-1
1
±
.4
PDU13F-2
2
±
.4
PDU13F-3
3
±
.5
PDU13F-5
5
±
.6
PDU13F-10
10
±
1.0
PDU13F-15
15
±
1.3
PDU13F-20
20
±
1.5
PDU13F-40
40
±
2.0
PDU13F-50
50
±
2.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
Incremental Delay
Total Delay
Change (ns)
3.5
±
1.0
7
±
1.0
14
±
1.0
21
±
1.1
35
±
1.8
70
±
3.5
105
±
5.3
140
±
7.0
280
±
14.0
350
±
17.5
2004 Data Delay Devices
Doc #97001
3/25/04
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDU13F-.5MC3 | 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
| PDU16F | Programmable 6-bit TTL delay line |
| PDU16F-1 | Programmable Delay Line |
| PDU16F-10 | Programmable Delay Line |
| PDU16F-2 | Programmable Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDU13F-5MC3 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) |
| PDU13FSERIES | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:3-BIT PROGRAMMABLE DELAY LINE |
| PDU14-.5 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Delay Line |
| PDU14-.5A4 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Delay Line |
| PDU14-.5B4 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Delay Line |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。