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參數(shù)資料
| 型號(hào)： | PDM41532SA12TITY |
| 廠商： | IXYS CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 230K |
| 代理商： | PDM41532SA12TITY |
PDM41532
6
Rev. 1.3 - 4/10/98
PRELIMINARY
AC Electrical Characteristics
NOTES: 1. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
.
2. t
HZCE
, t
HZOE
, and t
HZWE
are specified with C
L
= 5 pF as in Figure 2. Transition is measured
±
200 mV from
steady state voltage.
Description
–10
–12
–15
–20
READ Cycle
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
READ cycle time
t
RC
10
—
12
—
15
—
20
—
ns
Address access time
t
AA
—
10
—
12
—
15
—
20
ns
Chip enable access time
t
ACE
—
9
—
11
—
14
—
18
ns
Byte access time
t
BA
—
5
—
6
—
7
—
9
ns
Output hold from address change
t
OH
2
—
2
—
3
—
3
—
ns
Byte disable to output in low-Z
(1, 6)
t
LZBE
0
—
0
—
0
—
0
—
ns
Byte enable to output in high-Z
(1, 6)
t
HZBE
—
5
—
6
—
7
—
9
ns
Chip enable to output in low-Z
(1, 6)
t
LZCE
3
—
3
—
3
—
3
—
ns
Chip disable to output high-Z
(1, 6)
t
HZCE
—
5
—
6
—
7
—
9
ns
Output enable access time
t
AOE
—
5
—
6
—
7
—
9
ns
Output enable to output in low-Z
(1, 6)
t
LZOE
0
—
0
—
0
—
0
—
ns
Output disable to output in high-Z
(1, 6)
t
HZOE
—
5
—
6
—
7
—
9
ns
t
AA
t
RC
UB, LB
OE
CE
ADDRESSES
t
OH
t
AOE
t
BA
D
OUT
Output Data Valid
t
LZBE(6)
t
LZOE(6)
t
LZCE(6)
t
ACE
t
HZCE(6)
t
HZOE(6)
t
HZBE(6)
Read Cycle Timing Diagram
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