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參數(shù)資料
| 型號： | PDM41532LA15T |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO44 |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 368K |
| 代理商： | PDM41532LA15T |
PDM41532
Rev. 1.3 - 4/10/98
9
PRELIMINARY
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Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDR
VCC for Retention Data
2.5
—
5.5
V
ICCDR
Data Retention Current
CE
≥ V
CC – 0.2V
VIN ≥ VCC – 0.2V
or
≤ 0.2V
VCC = 2V
—
95
500
A
VCC = 3V
—
350
750
A
tCDR
Chip Deselect to Data Retention Time
0
—
ns
tR
(1)
Operation Recovery Time
tRC
——
ns
NOTES: 1. This parameter is determined by device characterization but is not production tested.
2. WE is HIGH for read cycles.
3. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high imped-
ance state.
4. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high imped-
ance state.
5. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.
6. Measured with CL = 5pF as in Figure 2. Transition is measured +200mv from steady state voltage.
Low VCC Data Retention Waveform
DON'T CARE
VCC
V
IH
IL
t CDR
V
t R
4.5V
Data Retention Mode
CE
DR
VDR
Data Retention Electrical Characteristics (LA Version Only)
NOTE: 1. This parameter is sampled.
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