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參數(shù)資料
| 型號： | PDI1394L40 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1394 enhanced AV link layer controller |
| 中文描述： | 1394增強影音鏈路層控制器 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394L40 |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
25
NOTE: The layout of the crystal portion of the PHY circuit is
important for obtaining the correct frequency, minimizing noise
introduced into the PHY’s Phase Lock Loop, and minimizing any
emissions from the circuit. The crystal and two load capacitors
should be considered as a unit during layout. The crystal and load
capacitors should be placed as close as possible to one another
while minimizing the loop area created by the combination of the
three components. Varying the size of the capacitors may help in
this. Minimizing the loop area minimizes the effect of the resonant
current (Is) that flows in this resonant circuit. This layout unit (crystal
and load capacitors) should then be placed as close as possible to
the PHY XI and XO terminals to minimize trace lengths.
SV01809
C9
C10
X1
Figure 12.
Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for
the design be to measure the frequency of the SYSCLK output of
the PHY. This should be done with a frequency counter with an
accuracy of 6 digits or better. If the SYSCLK frequency is more than
the crystal’s tolerance from 49.152 MHz, the load capacitance of the
crystal may be varied to improve frequency accuracy. If the
frequency is too high add more load capacitance; if the frequency is
too low decrease load capacitance. Typically, changes should be
done to both load capacitors (C9 and C10 above) at the same time,
and both should be of the same value. Additional design details and
requirements may be provided by the crystal vendor.
相關PDF資料 |
PDF描述 |
|---|---|
| PDI1394L40BE | 8349 TBGA NO PB W/O ENC |
| PDI1394P11 | 3-port physical layer interface |
| PDI1394P11BD | 3-port physical layer interface |
| PDI1394P25 | 1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 1-port 400 Mbps physical layer interface |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| PDI1394L40BE,551 | 制造商:NXP Semiconductors 功能描述:1394 A/V LINK LAYER - Trays |
| PDI1394L40BE,557 | 功能描述:視頻 IC DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| PDI1394L40BEGA | 功能描述:IC IEEE 1394 LINK CTRLR 144-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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