參數(shù)資料
型號(hào)： PDI1394L11
廠商： NXP Semiconductors N.V.
英文描述： 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器)
中文描述： 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器）
文件頁數(shù)： 30/46頁
文件大小： 294K
代理商： PDI1394L11
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
30
13.1.4
This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’
to the bit corresponding to the interrupt desired.
Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C
This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the
bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt
Acknowledge register.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
SV00275
31 30
Reset Value 0x00000000
Bits 18..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK).
13.1.5
Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the General Control Register.
Cycle Timer Register (CYCTM) – Base Address: 0x010
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
CYCLE_SECONDS
CYCLE_NUMBER
CYCLE_OFFSET
SV00276
3130
Reset Value 0x00000000
Bit 31..25:
Bit 24..12:
Bit 11..0:
R/W
R/W
R/W
Seconds count: 1-Hz cycle timer counter.
Cycle Number: 8kHz cycle timer counter.
Cycle Offset: 24.576MHz cycle timer counter.
13.1.6
This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register.
When reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid
when the PHYRRX bit (LNKPHYINTACK register bit 14) is set. Once this happens the register data is available in the PHYRXDATA, the
address of the register just read is also available in the PHYRXAD fields. When writing a Phy register, the address of the register to be written is
set in the PHYRGAD field and the data to be written to the register is set in PHYRGDATA, along with the WRPHY bit being set. Once the write
is complete, the WRPHY bit will be cleared. Do not write a new Read/Write command until the previous one has been completed. After the
Self-ID phase, PHY register 0 will be read automatically.
Phy Register Access (PHYACS) – Base Address: 0x014
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
SV00277
PHYRGAD
PHYRGDATA
PHYRXAD
PHYRXDATA
31 30
Reset Value 0x00000000
Bit 31:
R/W
Read Phy Chip Register: When asserted, the PDI1394L11 sends a read register request with address equal to
Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.
Write Phy Chip Register: When asserted, the PDI1394L11 sends a write register request with address equal to
Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.
Phy Chip Register Address: This is the address of the Phy-chip register that is to be accessed.
Phy Chip Register Data: This is the data to be written to the Phy-chip register indicated in Phy Rg Ad.
Phy Chip Register Received Address: Address of register from which Phy Rx Data came.
Phy Chip Register Received Data: Data from register addressed by Phy Rx Ad.
Bit 30:
R/W
Bit 27..24:
Bit 23..16:
Bit 11..8:
Bit 7..0:
R/W
R/W
R
R
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L11BA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller
PDI1394L11BA-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller
PDI1394L21 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
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