參數(shù)資料
型號： PCM9211PTR
廠商： TEXAS INSTRUMENTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, TOKEN RING TRANSCEIVER, PQFP48
封裝： GREEN, PLASTIC, LQFP-48
文件頁數(shù)： 66/121頁
文件大小： 1219K
代理商： PCM9211PTR
Clock/ Data
Recovery
MPIO_ A
SELECTOR
MPIO_ C
SELECTOR
MPIO _B
SELECTOR
MPIO _B 0(ASCKI 2)
MPIO _B 1(ABCKI 2)
MPIO _B 2(ALRCKI 2)
MPIO _B 3(ADIN2)
ADC
Com. Supply
MPO0/1
SELECTOR
MPO 0(TXOUT )
MPO 1(VOUT )
MAIN
OUTPUT
SCKO
BCK
LRCK
DOUT
PORT
RXIN8
RXIN9
RXIN10
RXIN11
DITOUT
AUTO
DIR
ADC
AUXIN0
AUXIN1
AUXIN2
AUTO
DIR
ADC
AUXIN0
AUXIN1
AUXIN2
AUTO
DIR
ADC
AUXIN0
AUXIN1
DIT
Lock :DIR
Unlock:ADC
AUXIN 2
AUXOUT
OSC
Divider
XMCKO
Divider
XMCKO
DITOUT
RECOUT 0
RECOUT 1
AUXIN 0
AUXIN1
ADC Standalone
ADC Mode
Control
Function
Control
REGISTER
EXTRA DIR FUNCTIONS
FILT
PLL
DIR
Lock Detection
ERROR/ INT0 (ERROR )
NPCM/INT1 (NPCM )
ADC Clock
(SCK /BCK/LRCK)
(To MPIO _A & MPO0/1 )
ADC
DIR CS
( 48-bit)
DIT CS
( 48-bit)
DIR Interrupt
GPIO/GPO
Data
MPIO_ A
MPIO_ B
MPIO_ C
MPO0
MPO1
Divider
( to MPIO_A )
Secondary BCK / LRCK
Selector
RECOUT0
RECOUT1
SBCK /SLRCK
DOUT
RXIN7
SCKO/ BCK/LRCK
RXIN 0
RXIN 1
RXIN 2
RXIN 4/ASCKI 0
RXIN 3
RXIN 5/ABCKI 0
RXIN 6/ALRCKI 0
RXIN 7/ADIN0
RXIN7
RXIN6
RXIN5
RXIN4
RXIN3
RXIN2
RXIN1
RXIN0
MPIO_ A0( CLKST )
MPIO_ A1( VOUT)
MPIO_ A2( XMCKO)
MPIO_ A3( INT0)
VINL
VINR
VCOM
MPIO _C0( TXSCK )
MPIO _C1( TXBCK )
MPIO _C2( TXLRCK )
MPIO _C3( TXDIN )
XTI
XTO
All Port
f Calculator
S
DIR
f Calculator
S
DIR
P and P
C
D
f Calculator
S
ERROR DETECTION
Non-PCM DETECTION
Flags
DTS-CD/LD Detection
Validity Flag
User Data
Channel Status Data
BFRAME Detection
Interrupt System
These pins are Hi-Z
at default.
www.ti.com
SBAS495 – JUNE 2010
Default Routing Function (After RESET)
The default routing paths are shown in Figure 32. MPIO_A0-A3 are selected by CLKST, VOUT, XMCKO, and
INT0. Note that by default, MPIO_A0-A3 pins are Hi-Z as set by Registers MPA0HZ, MPA1HZ, MPA2HZ, and
MPA3HZ.
Figure 32. Default Routing Block Diagram
By default, the ADC starts up as a clock slave to the crystal that is connected to the PCM9211. The DIR receives
data on RXIN2. When the DIR is unlocked, the ADC has priority, and uses the Main port. When the DIR is
locked, data from the MAIN PORT are DIR data.
Copyright 2010, Texas Instruments Incorporated
49
Product Folder Link(s): PCM9211
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