參數(shù)資料
型號： PCM3168ATPAPRQ1G4
廠商： Texas Instruments
文件頁數(shù)： 15/68頁
文件大?。?/td> 0K
描述： IC 24-BIT AUDIO CODEC 64-HTQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 6 / 8
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 107 / 112（差分），104 / 112（單端）
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-HTQFP（10x10）
包裝： 帶卷 (TR)
RESET OPERATION
VDD
0V
0.5
VCC
(VDD=3.3V,typ)
t
ADCDLY2
t
DACDLY2
Fade-In
ZERO
VCOMDA
(0.5
VCCDA1)
3846
SCKI
NormalOperation
SynchronousClocks
(VDD=2.2V,typ)
RST
InternalReset
VOUT1
to
VOUT8
±
DOUT1/2/3
SCKI,
BCKAD/DA,
LRCKAD/DA
t
ADCDLY1
t
DACDLY1
SBAS452 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
The PCM3168A and PCM3168A-Q1 have both an internal power-on reset circuit and an external reset circuit.
The sequences for both reset circuits are illustrated in Figure 33, Table 7, and Figure 34. Figure 33 and Table 7
describe the timing chart at the internal power-on reset. Initialization is triggered automatically at the point where
VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on if RST
is kept high and SCKI is provided. VOUT from the DACs are forced to the VCOMDA level initially (= 0.5 ×
VCCDA1) and settles at a specified level according to the rising VCC. If synchronization among SCKI,
BCKAD/DA, and LRCKAD/DA is maintained, VOUT starts to output with a fade-in sequence after tDACDLY1 from
the internal reset release; VOUT then provides an output that corresponds to DIN after (3846 SCKI + tDACDLY1 +
tDACDLY2) from power-on. Meanwhile, DOUT from the ADCs begins to output with a fade-in sequence after
tADCDLY1 from the internal reset release; DOUT then provides output corresponding to VIN after (3846 SCKI +
tADCDLY1 + tADCDLY2) from power-on. If the synchronization is not held, the internal reset is not released and both
operating modes are maintained at reset and power-down states; after the synchronization forms again, both the
DAC and ADC return to normal operation with the above sequences.
Figure 34 illustrates a timing chart at the external reset. RST accepts an external forced reset by RST = low, and
provides a device reset and power-down state that makes the lowest power dissipation state available in the
PCM3168A and PCM3168A-Q1. If RST goes from high to low under synchronization among SCKI, BCKAD/DA,
and LRCKAD/DA, the internal reset is asserted, all registers and memory are reset, and finally the PCM3168A
and PCM3168A-Q1 enter into all power-down states. At the same time, VOUT is immediately forced into the
AGNDDA1 level and DOUT becomes '0'. To begin normal operation again, toggle RST high; the same power-up
sequence as power-on reset shown in Figure 33 is performed.
The PCM3168A and PCM3168A-Q1 do not require particular power-on sequences for VCC and VDD; it allows
VDD on and then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings,
however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx and DOUTx.
Figure 33 illustrates the response for VCC on with VDD on.
Figure 33. Power-On-Reset Timing Requirements
Table 7. Timing Requirements for Figure 33
SYMBOL
DESCRIPTION
SINGLE
DUAL
QUAD
UNIT
DAC delay time internal reset release to
tDACDLY1
3600
7200
14400
Period of LRCKDA
VOUT start
tDACDLY2
DAC fade-in/fade-out time
2048
4096
8192
Period of LRCKDA
ADC delay time internal reset release to
tADCDLY1
4800
9600
N/A
Period of LRCKAD
DOUT start
tADCDLY2
ADC fade-in/fade-out time
2048
4096
N/A
Period of LRCKAD
22
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1
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