- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10957 > PCM3168APAP (Texas Instruments)IC 24-BIT AUDIO CODEC 64-HTQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PCM3168APAP |
| 寤犲晢锛� | Texas Instruments |
| 鏂囦欢闋佹暩(sh霉)锛� | 26/68闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC 24-BIT AUDIO CODEC 64-HTQFP |
| 妯欐簴鍖呰锛� | 160 |
| 椤炲瀷锛� | 闊抽牷绶ㄨВ纰煎櫒 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 24 b |
| ADC / DAC 鏁�(sh霉)閲忥細 | 6 / 8 |
| 涓夎绌嶅垎瑾�(di脿o)璁婏細 | 鏄� |
| S/N 姣旓紝妯欐簴 ADC / DAC (db)锛� | 107 / 112锛堝樊鍒嗭級锛�104 / 112锛堝柈绔級 |
| 鍕曟厠(t脿i)鑼冨湇锛屾婧� ADC / DAC (db)锛� | 107 / 112锛堝樊鍒嗭級锛�104 / 112锛堝柈绔級 |
| 闆诲 - 闆绘簮锛屾ā鎿細 | 4.5 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 | 3 V ~ 3.6 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 64-TQFP 瑁搁湶鐒婄洡 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 64-HTQFP锛�10x10锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1077 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | 296-23899-5 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�鐣跺墠绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�
REGISTER WRITE OPERATION
MS
MC
MDI
X
(1)
'0'
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
D7
D6
D5
D4
D3
D2
D1
D0
X
R/
W ADR6
REGISTER READ OPERATION
MS
MC
MDI
X
(1)
'1'
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Don'tCare(X)
R/
W ADR6
MDO
Hi-Z
D7
D6
D5
D4
D3
D2
D1
D0
SBAS452 鈥� SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com
Figure 48 shows the functional timing diagram for single write operations on the serial control port. MS is held at
a high state until a register must be written. To start the register write cycle, MS is set to a low state. 16 clocks
are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle
has been completed, MS is set high to latch the data into the indexed mode control register.
Also, the PCM3168A and PCM3168A-Q1 support multiple write operations in addition to single write operations,
which can be performed by sending the following N-times of the 8-bit register data after the first 16-bit register
address and register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation
can be accomplished by setting MS to a high state.
(1) X = Don't care.
Figure 48. Register Write Operation
Figure 49 shows the functional timing diagram for single read operations on the serial control port. MS is held at
a high state until a register must be read. To start the register read cycle, MS is set to a low state. 16 clocks are
then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight
bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for
the next write or read operation. MDO remains in a high impedance state except during the eight MC clock
periods of the actual data transfer.
(1) X = Don't care.
Figure 49. Register Read Operation
32
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): PCM3168A PCM3168A-Q1
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-B5X-IX-B1 | CONVERTER MOD DC/DC 5.2V 75W |
| VE-B5W-IX-B1 | CONVERTER MOD DC/DC 5.5V 75W |
| VE-B5V-IW-B1 | CONVERTER MOD DC/DC 5.8V 100W |
| PCM3168APAPR | IC 24-BIT AUDIO CODEC 64-HTQFP |
| VE-B5L-IW-B1 | CONVERTER MOD DC/DC 28V 100W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PCM3168APAPR | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,96/192kHz,6ch-in 8ch-out Aud CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| PCM3168APAPRG4 | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,96/192kHz,6ch-in 8ch-out Aud CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| PCM3168A-Q1 | 鍒堕€犲晢:TI 鍒堕€犲晢鍏ㄧū:Texas Instruments 鍔熻兘鎻忚堪:24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output |
| PCM3168ATPAPQ1 | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,6-In/8-Out Audio CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| PCM3168ATPAPRQ1 | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC 24B,6-In/8-Out Audio CODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�
