參數(shù)資料
型號： PCM3052ARTFG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 編解碼器
英文描述： PCM CODEC, PQCC32
封裝： GREEN, PLASTIC, VQFN-32
文件頁數(shù)： 28/47頁
文件大小： 776K
代理商： PCM3052ARTFG4
www.ti.com
PCM3052A
SLES160 – NOVEMBER 2005
Table 4. User-Programmable Mode Controls
FUNCTION
RESET DEFAULT
REGISTER
BIT(S)
Digital attenuation control, 0 dB to –63 dB in 0.5-dB
0 dB, no attenuation
65 and 66
AT1[7:0], AT2[7:0]
steps (DAC)
Mode control register reset (ADC and DAC)
Normal operation
67
MRST
System reset (ADC and DAC)
Normal operation
67
SRST
ADC power-save control (ADC)
Normal operation
67
ADPSV
DAC Power Save Control (DAC)
Normal operation
67
DAPSV
Soft-mute control (DAC)
Mute disabled
68
MUT[2:1]
Oversampling rate control (DAC)
64-fS oversampling
68
OVR1
De-emphasis function control (DAC)
De-emphasis disabled
69
DM12
De-emphasis sampling rate selection (DAC)
48 kHz
69
DMF[1:0]
Digital filter rolloff control (DAC)
Sharp rolloff
70
FLT0
Output phase select (DAC)
Normal
71
DREV
Multiplexer input channel control (ADC)
LINE IN
72
AML
PGA gain control (ADC)
–4 dB
72
PG[4:0]
HPF bypass control (ADC)
HPF enabled
75
BYP
DAC output control (DAC)
Disabled
77
DACMSK
Additional format information (DIT)
Two audio channels without pre-emphasis
77
AFI[5:3]
Copyright flag (DIT)
Asserted
77
COPY
Audio sample word type (DIT)
PCM
77
AUDIO
DIT output control (DIT)
Disable
77
DITMSK
Category code (DIT)
General
78
CAT[15:8]
Clock accuracy (DIT)
Level II
79
CLK[29:28]
Sampling frequency (DIT)
44.1kHz
79
SF[27:24]
Validity bit for L-channel (DIT)
Valid
80
VALIDL
Validity bit for R-channel (DIT)
Valid
80
VALIDR
S/PDIF output control (DIT)
Disabled
80
SPDIF
Word Length (DIT)
24 bits
80
WL[35:32]
Table 5. Register Map
REGISTER ADDRESS
DATA
IDX
REGIS-
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(B8–B14)
TER
41h
65
0
1
0
1
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
42h
66
0
1
0
1
0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
43h
67
0
1
0
1
MRST
SRST
ADPSV
DAPSV
RSV(1)
44h
68
0
1
0
1
0
RSV(1)
OVR1
RSV(1)
MUT2
MUT1
45h
69
0
1
0
1
0
1
RSV(1)
DMF1
DMF0
DM12
RSV(1)
46h
70
0
1
0
1
0
RSV(1)
FLT0
RSV(1)
1
RSV(1)
47h
71
0
1
0
1
RSV(1)
DREV
48h
72
0
1
0
1
0
RSV(1)
AML
PG4
PG3
PG2
PG1
PG0
4Bh
75
0
1
0
1
0
1
RSV(1)
BYP
1
RSV(1)
4Dh
77
0
1
0
1
0
1
DACMSK
RSV(1)
AFI5
AFI4
AFI3
COPY
AUDIO
DITMSK
4Eh
78
0
1
0
1
0
CAT15
CAT14
CAT13
CAT12
CAT11
CAT10
CAT9
CAT8
4Fh
79
0
1
0
1
RSV(1)
CLK29
CLK28
SF27
SF26
SF25
SF24
50h
80
0
1
0
1
0
VALIDL
VALIDR
SPDIF
RSV(1)
WL35
WL34
WL33
WL32
(1)
RSV means reserved for test operation or future extension, and these bits should be set 0 during regular operation. Do not write any
values in other addresses than those listed in the table.
34
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