37
VCC3
AGND3
VCC4
AGND4
NC
AGND6
VCC5
AGND5
NC
VCOM
VOUT1
VOUT2
25
24
RST
SCKI
SCKO
BCK
LRCK
TEST
VDD
DGND
DATA1
DATA2
DATA3
ZEROA
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
12
26
11
27
10
28
9
29
8
30
7
31
6
32
5
33
4
34
3
35
2
36
1
PT PACKAGE
(TOP VIEW)
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
V
O
U
T
6
V
O
U
T
5
V
O
U
T
4
V
O
U
T
3
ML
MC
MDI
MDO
NC
V
C
1
AGND1
V
C
2
AGND2
P0028-04
PCM1602A
SLES146A – AUGUST 2005 – REVISED OCTOBER 2010
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND1
27
–
Analog ground
AGND2
25
–
Analog ground
AGND3
23
–
Analog ground
AGND4
21
–
Analog ground
AGND5
17
–
Analog ground
AGND6
19
–
Analog ground
BCK
40
I
Shift clock input for serial audio data. Clock must be one of 32 fS, 48 fS, or 64 fS.
(1)
DATA1
45
I
Serial audio data input for VOUT1 and VOUT2
(1)
DATA2
46
I
Serial audio data input for VOUT3 and VOUT4
(1)
DATA3
47
I
Serial audio data input for VOUT5 and VOUT6
(1)
DGND
44
–
Digital ground
LRCK
41
I
Left and right clock input. This clock is equal to the sampling rate, fS.
(1)
MC
35
I
Shift clock for serial control port (2)
MDI
34
I
Serial data input for serial control port (2)
MDO
33
O
Serial data output for serial control port (3)
ML
36
I
Latch enable for serial control port (2)
(1)
Schmitt-trigger input, 5-V tolerant
(2)
Schmitt-trigger input with internal pulldown, 5-V tolerant
(3)
3-state output
6
Copyright 2005–2010, Texas Instruments Incorporated