- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369950 > PCKV857ADGG (NXP SEMICONDUCTORS) 100-250 MHz differential 1:10 clock driver PDF資料下載
參數(shù)資料
| 型號(hào)： | PCKV857ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100-250 MHz differential 1:10 clock driver |
| 中文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 101K |
| 代理商： | PCKV857ADGG |
Philips Semiconductors
Product data
PCKV857A
100-250 MHz differential 1:10 clock driver
2003 Jul 31
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
IK
Input voltage, all inputs
V
DDQ
= 2.3 V, I
I
= -18 mA
V
DDQ
= min to max, I
OH
= -1 mA
V
DDQ
= 2.3 V, I
OH
= -12 mA
V
DDQ
= min to max, I
OL
= 1 mA
V
DDQ
= 2.3 V, I
OL
= 12 mA
V
DDQ
= 2.7 V, V
I
= 0 V to 2.7 V
V
DDQ
= 2.7 V, V
O
= V
DDQ
or GND
CLK and CLK = 0 MHz,
PWRDWN = LOW;
Σ
of I
DD
and AI
DD
f
O
= 67 MHz to 190 MHz
f
O
= 67 MHz to 190 MHz
V
CC
= 2.5 V, V
I
= V
CC
or GND
—
—
1.2
V
V
DDQ
0.1
1.7
—
—
V
V
OH
HIGH-level output voltage
—
—
V
—
—
0.1
V
V
OL
LOW-level output voltage
—
—
0.6
V
I
I
Input current
—
—
±
10
±
10
μ
A
μ
A
I
OZ
HIGH-impedance-state output current
—
—
I
DDPD
Power-down current on V
DDQ
+ AV
DD
—
30
100
μ
A
I
DD
AI
DD
C
I
Dynamic current on V
DDQ
Supply current on AV
DD
Input capacitance
—
200
300
mA
—
8
10
mA
2
2.8
3
pF
NOTE:
1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs.
2. All typical values are at respective nominal V
DDQ
.
3. Differential cross-point voltage is expected to track variations of V
DDQ
and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
PARAMETER
MIN
MAX
UNIT
f
CK
Operating clock frequency
100
250
MHz
Input clock duty cycle
40
60
%
Stabilization time
1
100
—
μ
s
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCKV857ADGV | 100-250 MHz differential 1:10 clock driver |
| PCL-240K | Pulse Generator |
| PCL2004A3K | |
| PCL2004AB | |
| PCL2004ALP | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCKV857ADGG,512 | 功能描述:鎖相環(huán) - PLL 70-190MHZ 2.5V DIF1:10 CLK DRV RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCKV857ADGG,518 | 功能描述:鎖相環(huán) - PLL 70-190MHZ 2.5V DIF1:10 CLK DRV RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCKV857ADGV | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:100-250 MHz differential 1:10 clock driver |
| PCKV857ADGV,112 | 功能描述:鎖相環(huán) - PLL 70-190MHZ 2.5V DIF1:10 CLK DRV RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCKV857ADGV,118 | 功能描述:鎖相環(huán) - PLL 70-190MHZ 2.5V DIF1:10 CLK DRV RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。