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參數資料
| 型號： | PCK2022RADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK00 (100/133 MHz) spread spectrum differential system clock generator |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數： | 13/14頁 |
| 文件大?。?/td> | 100K |
| 代理商： | PCK2022RADGG |
Philips Semiconductors
Product data
PCK2022RA
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2003 Jul 31
8
AC ELECTRICAL CHARACTERISTICS
VDD3 = 3.3 V ±5%; fcrystal = 14.31818 MHz
Host clock outputs
Tamb = 0 to +70 °C; see Figure 1 for waveforms and Figure 6 for test setup.
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNITS
NOTES
MIN
MAX
MIN
MAX
tPKP
HOST CLK average period
7.5
7.65
10.0
10.2
ns
11, 14, 20
Abs Min Period
Absolute minimum host clock period
7.35
N/A
9.85
N/A
ns
11, 14, 20
tRISE
HOST CLK rise time
175
700
175
700
ns
11, 15, 20
tFALL
HOST CLK fall time
175
700
175
700
ps
11, 15, 20
tJITTER
HOST_CLK cycle-to-cycle jitter
—
150
—
150
ps
11, 12, 14, 20
DUTY CYCLE
Output duty cycle
45
55
45
55
%
11, 14, 20
tSKEW
HOST CLK pin-to-pin skew
—
150
—
150
ps
11, 14, 20
Rise/Fall Match-
ing
Rise and Fall time matching
—
20%
—
20%
11, 16, 20
Vcrossover
40% VOH
55% VOH
40% VOH
55% VOH
V
11, 14, 20
REFER TO NOTES ON PAGE 9.
IOCLK outputs
Tamb = 0 to +70 °C
LIMITS
SYMBOL
PARAMETER
33 MHz MODE
66 MHz MODE
UNITS
NOTES
MIN
MAX
MIN
MAX
tPKP
IOCLK period
30.0
N/A
15.0
N/A
ns
2, 3, 9, 20
tPKH
IOCLK HIGH time
12.0
N/A
6.0
N/A
ns
5, 10, 20
tPKL
IOCLK LOW time
12.0
N/A
6.0
N/A
ns
6, 10, 20
tRISE
IOCLK rise time
0.5
2.0
0.5
2.0
ns
8, 20
tFALL
IOCLK fall time
0.5
2.0
0.5
2.0
ns
8, 20
tJITTER
Cycle-to-cycle jitter
—
200
—
200
ps
18, 20
DUTY CYCLE
Output duty cycle
45
55
45
55
%
18, 20
REFER TO NOTES ON PAGE 9.
USB clock output, 48MHz
Tamb = 0 to +70 °C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
PARAMETER
48 MHz MODE
UNITS
NOTES
MIN
MAX
f
Frequency, actual
48.08
MHz
4
fD
Deviation from 48 MHz
+167
ppm
4
tHKL
3V48MHZCLK LOW time
5.05
N/A
ns
20
tRISE
3V48MHZCLK rise time
1.0
4.0
ns
8, 20
tFALL
3V48MHZCLK fall time
1.0
4.0
ns
8, 20
tJITTER
Cycle-to-cycle jitter
—
250
ps
18, 20
DUTY CYCLE
Output duty cycle
45
55
%
18, 20
REFER TO NOTES ON PAGE 9.
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相關代理商/技術參數 |
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| PCK2022RDGG | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK00 100/133 MHz spread spectrum differential system clock generator |
| PCK2023 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CK408 66/100/133/200 MHz spread spectrum differential system clock generator |
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| PCK2023DL | 功能描述:鎖相環(huán) - PLL WIT -CHG 112 TO 512 PCK METHOD RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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