- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369950 > PCK2000MDB (NXP SEMICONDUCTORS) CK97 66/100MHz Mobile System Clock Generator PDF資料下載
參數(shù)資料
| 型號： | PCK2000MDB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK97 66/100MHz Mobile System Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 81K |
| 代理商： | PCK2000MDB |
Philips Semiconductors
Product specification
PCK2000M
CK97 (66/100MHz) Mobile System Clock Generator
1998 Sep 29
8
ALL CLOCK OUTPUTS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
T
amb
= 0
°
C to +70
°
C
MIN
1.0
1.0
UNIT
NOTES
MAX
8.0
8.0
T
PZL
, T
PZH
T
PLZ
, T
PHZ
Output enable time
Output disable time
ns
ns
NOTES:
1. See Figure 3 for measure points.
2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.
4. The CPUCLK must always lead the PCICLK as shown in Figure 2.
5. T
HKH
is measured @ 2.0V as shown in Figure 4.
6. T
HKL
is measured @ 0.4V as shown in Figure 4.
7. The time is specified from when V
DDQ
achieves its nominal operating level (typical condition is V
DDQ
= 3.3V) until the frequency output is
stable and operating within specification.
8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.
9. T
HRISE
and T
HFALL
are measured as a transition through the threshold region V
= 0.4V and V
= 2.0V (1mA) JEDEC specification.
10.T
HRISE
and T
HFALL
(REF, PCI) are measured as a transition through the threshold region V
OL
= 0.4V and V
OH
= 2.4V
AC WAVEFORMS
V
M
= 1.25V @ V
DDQ2
and 1.5V @ V
DDQ3
V
X
= V
OL
+ 0.3V
V
Y
= V
OH
–0.3V
V
and V
OH
are the typical output voltage drop that occur with the
output load.
CPUCLK
1.25V
SW00240
1.25V
CPUCLK
V
DDQ2
V
SS
V
DDQ2
V
SS
T
HSKW
Figure 1. CPUCLK to CPUCLK skew
CPUCLK
1.5V
1.25V
PCICLK
V
DDQ2
V
SS
V
DDQ3
V
SS
T
HPOFFSET
SW00241
Figure 2. CPUCLK to PCICLK offset
SW00242
T
DUTY CYCLE
T
HKH
T
RISE
T
FALL
T
HKL
T
PKP
T
PKH
T
RISE
T
FALL
T
PKL
2.5V CLOCKING
INTERFACE
3.3V CLOCKING
INTERFACE
(TTL)
2.0
1.25
0.4
2.4
1.5
0.4
Figure 3. 2.5V/3.3V Clock waveforms
相關PDF資料 |
PDF描述 |
|---|---|
| PCK2001MDB | 14.318-150 MHz I2C 1:10 Clock Buffer |
| PCK2002M | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002MDB | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002MPW | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002P | 140 MHz PCI-X clock buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2000MDB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| PCK2001 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14.318-150 MHz I2C 1:18 Clock Buffer |
| PCK2001DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14.318-150 MHz I2C 1:18 Clock Buffer |
| PCK2001DL,112 | 功能描述:時鐘緩沖器 PII CLOCK DRIVER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK2001DL,118 | 功能描述:時鐘緩沖器 PII CLOCK DRIVER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。