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參數(shù)資料
| 型號： | PCK2000MDB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | CK97 66/100MHz Mobile System Clock Generator |
| 中文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 81K |
| 代理商： | PCK2000MDB |
Philips Semiconductors
Product specification
PCK2000M
CK97 (66/100MHz) Mobile System Clock Generator
1998 Sep 29
3
PIN DESCRIPTION
PIN NUMBER
SYMBOL
REF
V
SSREF
V
DDREF
XTAL_IN
XTAL_OUT
V
SSPCI
[0–1]
PCICLK_F
V
DDPCI
[0–1]
PCICLK [1–5]
V
DDCORE
[0–1]
V
SSCORE
[0–1]
SEL
FUNCTION
26
28
27
1
2
3, 12
4
6, 9
14.318 MHz clock output
GROUND for REF output
POWER for REF output
14.318 MHz crystal input
14.318 MHz crystal output
GROUND for PCI outputs
Free-running PCI output
POWER for PCI outputs
PCI clock outputs.
Isolated POWER for core
Isolated GROUND for core
Logic select pins
Select pin for enabling 66 MHz or 100MHz or 66 MHz. L = 66 Mhz
H = 100MHz
Control pin to put device in powerdown state, active low
Control pin to disable CPU clocks, active low
Control pin to disable PCI clocks, active low
Power for CPU outputs
GROUND for CPU outputs
CPU and Host clock outputs 2.5V
5, 7, 8, 10, 11
13, 21
14, 20
16
15
SEL100/66
17
18
19
25
22
PWRDWN
CPUSTOP
PCISTOP
V
DDCPU
V
SSCPU
CPUCLK [0–1]
23, 24
NOTE:
1. V
and V
names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DDCPU
pins tied to a 2.5V supply, all remaining V
DD
pins
tied to a common 3.3V supply and all V
SS
pins being common.
BLOCK DIAGRAM
PWRDWN
LOGIC
STOP
LOGIC
STOP
LOGIC
PLL1
14.318
MHZ
OSC
PWRDWN
LOGIC
LOGIC
SW00275
X
X
X
X
X
X
X
X
X
X
X
REFCLK (14.318 MHz)
PWRDWN
PCISTOP
CPUSTOP
SEL0
SEL100/66
XTAL_IN
XTAL_OUT
CPUCLK [0–1]
PCICLK_F (33MHz)
PCICLK [1–5] (33MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCK2001MDB | 14.318-150 MHz I2C 1:10 Clock Buffer |
| PCK2002M | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002MDB | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002MPW | 0-300 MHz I2C 1:10 clock buffer |
| PCK2002P | 140 MHz PCI-X clock buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2000MDB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| PCK2001 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14.318-150 MHz I2C 1:18 Clock Buffer |
| PCK2001DL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:14.318-150 MHz I2C 1:18 Clock Buffer |
| PCK2001DL,112 | 功能描述:時鐘緩沖器 PII CLOCK DRIVER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PCK2001DL,118 | 功能描述:時鐘緩沖器 PII CLOCK DRIVER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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