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參數(shù)資料
| 型號(hào)： | PCK12429 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 25-400 MHz differential PECL clock generator |
| 中文描述： | 25-400 MHz的差分PECL時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | PCK12429 |
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Philips Semiconductors
Product data
PCK12429
25–400 MHz differential PECL clock generator
2002 Jun 03
9
Power supply filtering
The PCK12429 is a mixed analog/digital product and as such it
exhibits some sensitivities that would not necessarily be seen on a
fully digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power supply
pins. The PCK12429 provides separate power supplies for the
digital circuitry (V
CC
) and the internal PLL (PLL_V
CC
) of the device.
The purpose of this design technique is to try and isolate the high
switching noise digital outputs from the relatively sensitive internal
analog phase-locked loop. In a controlled environment such as an
evaluation board, this level of isolation is sufficient. However, in a
digital system environment where it is more difficult to minimize
noise on the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply filter on
the PLL_V
CC
pin for the PCK12429.
Figure 3 illustrates a typical power supply filter scheme. The
PCK12429 is most susceptible to noise with spectral content in the
1 kHz to 2 MHz range. A good choice of pole placement should be
close to 32 kHz. Therefore the filter should be designed to target this
range. The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the V
CC
supply and the PLL_V
CC
pin of the PCK12429. From the data sheet
the I
PLL_VCC
current (the current sourced through the PLL_V
CC
pin)
is typically 15 mA (20 mA maximum), assuming that a minimum of
3.0 V must be maintained on the PLL_V
CC
pin, very little DC voltage
drop can be tolerated when a 3.3 V V
CC
supply is used. The resistor
shown in Figure 3 must have a resistance of 10–15
to meet the
voltage drop criteria. The RC filter pictured will provide a broadband
filter with approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the series
resonant point of an individual capacitor, its overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well above the
bandwidth of the PLL.
V
CC
SW00745
PLL_V
CC
PCK12429
0.01
μ
F
22
μ
F
R
S
= 10–15
L = 1000
μ
H
R = 15
3.3 V
3.3 V
Figure 3. Power supply filter
A higher level of attenuation can be achieved by replacing the
resistor with an appropriate valued inductor. Figure 3 shows a
1000
μ
H choke, this value choke will show a significant impedance
at 10 KHz frequencies and above. Because of the current draw and
the voltage that must be maintained on the PLL_V
CC
pin, a low DC
resistance inductor is required (less than 15
). Generally the
resistor/capacitor filter will be cheaper, easier to implement, and
provide an adequate level of supply filtering.
The PCK12429 provides sub-nanosecond output edge rates, and
thus a good power supply bypassing scheme is a must. Figure 4
shows a representative board layout for the PCK12429. There exists
many different potential board layouts and the one pictured is but
one. The important aspect of the layout in Figure 4 is the low
impedance connections between V
CC
and GND for the bypass
capacitors. Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective capacitor
resonances at frequencies adequate to supply the instantaneous
switching current for the PCK12429 outputs. It is imperative that low
inductance chip capacitors are used; it is equally important that the
board layout does not introduce back all of the inductance saved by
using the leadless capacitors. Thin interconnect traces between the
capacitor and the power plane should be avoided and multiple large
vias should be used to tie the capacitors to the buried power planes.
Fat interconnect and large vias will help to minimize layout induced
inductance and thus maximize the series resonant point of the
bypass capacitors.
SW00746
Xtal
1
C3
C2
é
é
é
= VCC
= GND
= Via
éé
é
é
C1
ééé
éé
éé
C1
R1 = 10–15
C1 = 0.01
μ
F
C2 = 22
μ
F
C3 = 0.1
μ
F
R1
Figure 4. PCB board layout for PCK12429
Note the dotted lines circling the crystal oscillator connection to the
device. The oscillator is a series resonant circuit and the voltage
amplitude across the crystal is relatively small. It is imperative that
no actively switching signals cross under the crystal, as crosstalk
energy coupled to these lines could significantly impact the jitter of
the device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the crystal
and the on-board oscillator.
Although the PCK12429 has several design features to minimize the
susceptibility to power supply noise (isolated power and grounds
and fully differential PLL) there still may be applications in which
overall performance is being degraded due to system power supply
noise. The power supply filter and bypass schemes discussed in this
section should be adequate to eliminate power supply noise related
problems in most designs.
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| PCK12429BD | 25-400 MHz differential PECL clock generator |
| PCK12429D | 25-400 MHz differential PECL clock generator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK12429A | 功能描述:鎖相環(huán) - PLL 25-400 MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK12429A,112 | 功能描述:鎖相環(huán) - PLL 25-400 MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK12429A,118 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 25-400 MHZ DIFF PECL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429A-T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 25-400 MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PCK12429BD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 25-400MHZ DIFF PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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