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參數(shù)資料
| 型號(hào)： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 32/192頁(yè) |
| 文件大?。?/td> | 1551K |
| 代理商： | PCI9060ES |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 23
Version 1.02
3.6.2 Direct Slave Operation (PCI Master to
Local Bus Access)
PCI 9080 supports both burst memory mapped transfer
accesses and I/O-mapped, single-transfer accesses to
the local bus from the PCI bus. PCI Base Address
registers are provided to set up the location of the
adapter in PCI memory and I/O space. In addition, local
mapping registers allow address translation from PCI
address space to Local Address Space. There are three
spaces available:
Space 0
Space 1
Expansion ROM space
Expansion ROM space is intended to support a bootable
ROM device for the host. Each local space can be
programmed to operate 8 bit, 16 bit, or 32 bit local bus
width. PCI 9080 has an internal wait state generator and
external wait state input (READYi#). READYi# can be
disabled or enabled with the internal configuration
register. The local bus, independent of the PCI bus, can
Burst as long as data is available (Continuous Burst
mode)
Burst four Lwords at a time
Perform continuous single cycle, with or without wait
state(s)
For single cycle Direct Slave reads, PCI 9080 reads a
single local bus Lword or partial Lword. PCI 9080
disconnects after one transfer for all Direct Slave I/O
accesses.
For the highest data transfer rate, PCI 9080 supports
posted write and can be programmed to prefetch data
during PCI Burst Read. The prefetch size, when
enabled, can be one to 16 Lwords, or until the PCI stops
requesting. PCI 9080 will prefetch if enabled and drop
the local bus after the prefetch counter is reached. In a
continuous prefetch mode, PCI 9080 prefetches as long
as any FIFO space is available and terminates the
prefetch when the PCI terminates the request. If read
prefetching is disabled, PCI 9080 disconnects after one
read transfer.
3.6.2.1 PCI 2.1 Mode
PCI 9080 can be programmed through the Local
Arbitration and PCI Mode Register to perform delayed
reads, as specified in PCI specification v2.1.
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Figure 3-9. PCI Specification v2.1 Delayed Reads
In addition to delayed read, PCI 9080 supports the
following in PCI specification v2.1 features.
No write while read is pending (RETRY for reads)
Write and flush pending read
PCI 9080 also supports Read Ahead mode (refer to
Figure 3-10), where prefetched data can be read from
the PCI 9080 internal FIFO instead of from the local
side. The address must be subsequent to the previous
address and must be 32-bit aligned (next address =
current address + 4).
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Figure 3-10. PCI 9080 Read Ahead Mode
PCI 9080 can be programmed to keep the PCI bus by
generating a wait state(s), de-asserting TRDY#, if write
FIFO becomes full. PCI 9080 can also be programmed
to keep the local bus, LHOLD is asserted, if Direct Slave
Write FIFO becomes empty or the Direct Slave Read
FIFO becomes full. The local bus is dropped in either
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
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