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89
8.9
Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 87 for a complete
description of the register contents.
Bit
Name
Type
Default
31
30
29
28
27
26
25
24
Bus options
R
0
23
22
21
20
19
18
17
16
RW
X
RW
X
RW
X
RW
X
RW
0
R
0
R
0
RW
X
RW
X
RW
X
RW
X
RW
X
RW
X
RW
X
RW
X
Bit
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bus options
R
0
RW
1
RW
0
RW
1
RW
0
R
0
R
0
R
0
RW
X
RW
X
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Default:
Bus options
20h
Read/Write, Read-only
X0XX A0X2h
Table 87. Bus Options Register Description
BIT
31
FIELD NAME
irmc
TYPE
RW
DESCRIPTION
Isochronous resource-manager capable. IEEE 1394 bus-management field. Must be valid when
bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16)
is set to 1. Default value for this bit is 0.
30
cmc
RW
Cycle master capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in
the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. Default value
for this bit is 0.
29
isc
RW
Isochronous support capable. IEEE 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set
to 1. Default value for this bit is 0.
28
bmc
RW
Bus manager capable. IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in
the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. Default value
for this bit is 0.
27
pmc
RW
Power-management capable. IEEE 1394 bus-management field. When bit 27 is set to 1, this
indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the
host controller control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. Default value
for this bit is 0.
Reserved. Bits 2624 return 0s when read.
Cycle master clock accuracy, in parts per million. IEEE 1394 bus-management field. Must be valid
when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see
Section 8.16) is set to 1. Default value for this field is 00h.
2624
2316
RSVD
cyc_clk_acc
R
RW
1512
max_rec
RW
Maximum request. IEEE 1394 bus-management field. Hardware initializes this field to indicate the
maximum number of bytes in a block request packet that is supported by the implementation. This
value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software may
change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 8.16) is set to 1. A received block write request
packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not
affected by a software reset, and defaults to value indicating 2048 bytes on a system (hardware)
reset. Default value for this field is Ah.
118
76
RSVD
g
R
Reserved. Bits 118 return 0s when read.
Generation counter. This field is incremented if any portion of the configuration ROM has been
incremented since the prior bus reset.
RW
53
20
RSVD
Lnk_spd
R
R
Reserved. Bits 53 return 0s when read.
Link speed. This field returns 010, indicating that the link speeds of 100M bits/s, 200M bits/s, and
400M bits/s are supported.
These bits are cleared only by the assertion of GRST.