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參數(shù)資料
| 型號： | PCI2050A |
| 英文描述： | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| 中文描述： | 32位。 66MHz的。 9主PCI至PCI橋 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050A |
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
secondary PCI address and data terminals
TERMINAL
NAME
I/O
DESCRIPTION
NO.
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
I/O
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on the
secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31
–
S_AD0 contain a
32-bit address or other destination information. During the data phase, S_AD31
–
S_AD0 contain data.
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
194
180
167
149
I/O
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a secondary bus PCI cycle, S_C/BE3
–
S_C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths
of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0 (S_AD7
–
S_AD0), S_C/BE1
applies to byte 1 (S_AD15
–
S_AD8), S_C/BE2 applies to byte 2 (S_AD23
–
S_AD16), and S_C/BE3 applies
to byte 3 (S_AD31
–
S_AD24).
S_DEVSEL
175
I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a PCI
master on the secondary bus, the bridge monitors S_DEVSEL until a target responds. If no target responds
before time-out occurs, then the bridge terminates the cycle with a master abort.
S_FRAME
179
I/O
Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is asserted
to indicate that a bus transaction is beginning and data transfers continue while S_FRAME is asserted. When
S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
19
18
17
16
15
14
13
11
10
O
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used to grant
potential secondary PCI bus masters access to the bus. Ten potential masters (including the bridge) can be
located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0 is reconfigured as an external secondary bus request signal
for the bridge.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI2050APDV | 功能描述:外圍驅(qū)動器與原件 - PCI 32B 66MHz 9-Master PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI2050APDVG4 | 功能描述:外圍驅(qū)動器與原件 - PCI 32B 66MHz 9-Master PCI-to-PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI2050B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PCI-TO-PCI BRIDGE |
| PCI2050BGHK | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-TO-PCI BRIDGE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI2050BIGHK | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-TO-PCI BRIDGE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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