參數(shù)資料
型號: PCI2050A
英文描述: 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
中文描述: 32位。 66MHz的。 9主PCI至PCI橋
文件頁數(shù): 11/17頁
文件大小: 220K
代理商: PCI2050A
PCI2050A
PCI-to-PCI BRIDGE
SCPS067
MAY 2001
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
bridge configuration header
The bridge configuration header for PCI2050A is exactly the same as the bridge configuration header for PCI2050
except for the following registers.
The PCI2050A bridge is a single-function PCI device. The configuration header is in compliance with the
PCI-to-PCI
Bridge Specification 1.1
. Table 1 shows the PCI configuration header, which includes the predefined portion of the
bridge configuration space. The PCI configuration offset is shown in the right column under the OFFSET heading.
Table 1. Bridge Configuration Header
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
Revision ID
08h
BIST
Header type
Primary latency timer
Cache line size
0Ch
Base address 0
10h
Base address 1
14h
Secondary bus latency timer
Subordinate bus number
Secondary bus number
Primary bus number
18h
Secondary status
I/O limit
I/O base
1Ch
Memory limit
Memory base
20h
Prefetchable memory limit
Prefetchable memory base
24h
Prefetchable base upper 32 bits
28h
Prefetchable limit upper 32 bits
2Ch
I/O limit upper 16 bits
I/O base upper 16 bits
30h
Reserved
Capability pointer
34h
Expansion ROM base address
38h
Bridge control
Interrupt pin
Interrupt line
3Ch
Arbiter control
Extended diagnostic
Chip control
40h
Reserved
44h
60h
GPIO input data
GPIO output enable
GPIO output data
P_SERR event disable
64h
Reserved
P_SERR status
Secondary clock control
68h
Reserved
6Ch
D8h
Power management capabilities
PM next item pointer
PM capability ID
DCh
Data
PMCSR bridge support
Power management control/status
E0h
Reserved
Hot swap control status
HS next item pointer
HS capability ID
E4h
Reserved
E8h
EFh
Reserved
Diagnostics
F0
Reserved
F4
FF
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