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參數(shù)資料
| 型號(hào)： | PCF5001T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | POCSAG Paging Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AE, SOT-136-1, SOP-28 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 273K |
| 代理商： | PCF5001T |
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1997 Mar 04
12
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
Fig.6 Status change in display pager mode.
INTERNAL
STATUS
IE
ON
SK
t
t
t
STP
STD
STD
tIEH
tSTH
MCD457 - 1
Fig.7 Status interrogation in display pager mode.
MCD458
IE
SR
t
t
t
t
t
STP
STH
SPD
IEH
STH
7.4
Decoding of the POCSAG data stream
The POCSAG coded input data stream is first noise filtered
by a digital filter. From the filtered data a sampling clock
synchronous to the data rate is derived. The PCF5001
supports 512 bits/s and 1200 bits/s data rates. This results
in a 512 Hz or 1200 Hz sampling clock frequency,
respectively. Synchronization on the POCSAG code
structure is performed using the improved Philips
ACCESS
algorithm, which employs a state machine with
six internal states.
A data rate of 2400 bits/s is possible if an external clock
generator of 153.6 kHz is connected to X1. The minimum
supply voltage is then
1.8 V.
The receiver enable output is activated a period equal to
t
RXON
before the input data is actually needed. The
decoder has first to achieve bit and word synchronization
before it can receive calls. The algorithm searches first for
the preamble and then for synchronization codeword
patterns.
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