參數(shù)資料
型號(hào)： PCF5001H
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： POCSAG Paging Decoder
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù)： 26/44頁(yè)
文件大?。?/td> 273K
代理商： PCF5001H
1997 Mar 04
26
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
7.19
EEPROM Write operation
The
program
mode is entered in OFF status by setting the
PD input LOW and the PS input HIGH at any time.
The ‘program’ mode is left and normal operation resumed
by either removing the power supply or setting the PD
input HIGH after the 38
th
data bit while continuing to clock
the PS input. The three EEPROM arrays can be
programmed in any order. Selection of array is made
during the second and third pulse on the PS input.
The ‘program’ mode has to be left after programming of
each array.
After entering the ‘program’ mode, keeping input PD LOW
during the first pulse on PS selects Memory Write
operation. After selection of the current array an erase
cycle of duration t
PEW
has to be carried out, during which
the supply voltage at V
SS
input must be at least V
PG
.
Program data for the selected array is entered bit by bit
using PD as data input and the rising edge on PS as data
strobe pulse. See Fig.19 for timing during an EEPROM
write operation.
After the last bit a special write cycle of duration t
PEW
has
to be carried out again, during which the supply voltage at
V
SS
input must be V
PG
. During conditions when the supply
voltage is increased to V
PG
the maximum DC ratings at V
ref
must not be exceeded. When the on-chip voltage
converter is enabled a voltage regulator diode or a
damping resistor of sufficiently low impedance has to be
connected between V
ref
and V
SS
to limit the voltage level
at V
ref
during program operation.
7.20
EEPROM Read operation
After entrance to the ‘program’ mode, keeping input PD
HIGH during the first pulse on PS selects Memory Read
operation. After selection of the current array the
programmed data is output bit-by-bit using PD as data
output. A positive edge on PS input switches to the next
bit. See Fig.19 for timing during an EEPROM read
operation.
7.21
Read-back operation via Microcontroller
Interface
In ‘display pager’ mode, the PCF5001 is capable of
delivering the EEPROM contents to an external
microcontroller using the serial interface outputs DO and
DS. The EEPROM data transfer mode is selected by
applying a LOW to input ON and a HIGH to input SK while
pulsing the SR input, and the interface is enabled (IE is
HIGH). The data transfer is started by a logic HIGH level
on SR. The HIGH level on SR must be removed before the
end of the tenth output byte, otherwise the transfer is
aborted and restarted. The minimum pulse duration
corresponds with t
SPD
in the status interrogation timing
(see Fig.7). The transfer is organized as 15-byte transfers.
The contents of each array are extended to 40 bits by
trailing zeros. The EEPROM data transfer starts with array
1, bit 0. A valid data bit at DO is indicated by a LOW-level
on DS as shown in Fig.20.
During EEPROM Read-back operation, the PCF5001
configuration and the outputs FL, OL are undefined.
After completion of the Read-Back operation, the
PCF5001 will re-enter the programmed configuration.
7.22
Voltage converter
The PCF5001 contains a switched capacitor-type on-chip
voltage converter, which can provide doubled supply
voltage to the external microcontroller and display control
devices. The microcontroller interface signals are level
shifted accordingly.
A capacitor of 100 nF (C
S
) must be connected between
pins CP and CN while a load capacitor of 10
μ
F is
connected to V
ref
as shown in Fig.23. The voltage
converter operates in ‘display pager’ mode only, when
enabled by programming SPF08 (see Table 9).
相關(guān)PDF資料
PDF描述
PCF5001T POCSAG Paging Decoder
PCF50603 Controller for power supply and battery management
PCF50603HN Controller for power supply and battery management
PCF50732 Baseband and audio interface for GSM
PCF50732H Baseband and audio interface for GSM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCF5001T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:POCSAG Paging Decoder
PCF5001TD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
PCF5001TD-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
PCF5012 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CODEC， Single
PCF5012A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CODEC， Single
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*