1997 Apr 04
30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
11 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
The PCF2113x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines E, RS,
and R/W are required. See Chapter 7.
In 4-bit mode data is transferred in two cycles of 4 bits
each using pins DB7 to DB4 for transaction. The higher
order bits (corresponding to DB7 to DB4 in 8-bit mode) are
sent in the first cycle and the lower order bits (DB3 to DB0
in 8-bit mode) in the second. Data transfer is complete
after two 4-bit data transfers. Note that two cycles are also
required for the Busy Flag check. 4-bit operation is
selected by instruction. See Figs 14 to 17 for examples of
bus protocol.
In 4-bit mode pins DB3 to DB0 must be left open-circuit.
They are pulled up to V
DD
internally.
12 INTERFACE TO MICROCONTROLLER
(I
2
C-BUS INTERFACE)
12.1
Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a Serial Clock Line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition.
12.2
I
2
C-bus protocol
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I
2
C-bus configuration for the different
PCF2113x read and write cycles is shown in
Figs 23 and 24. The slow down feature of the I
2
C-bus
protocol (receiver holds SCL low during internal
operations) is not used in the PCF2113x.
12.3
Definitions
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-Master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.